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These last days I've been busy reading the code from nukeykt's Verilog recreation based on the VDP decap trying to figure out how the Mega Drive VDP works and started to notice some oddities regarding SMS mode (especially when trying to use mode 5).

Just to make it clear, I haven't been able to verify this myself (I don't have the suitable hardware at hand), so it may be better if somebody here checks this on actual hardware to make sure.

In case some users here aren't aware with all these terms as they're largely Mega Drive specific:

SMS mode: console is in Master System compatibility mode
MD mode: console is in Mega Drive mode
Mode 4: VDP is in the Master System graphics mode
Mode 5: VDP is in the Mega Drive graphics mode

VDP commands in mode 5

Under mode 4, VDP commands are 16-bit. Under MD mode this means writing one word to the control port, while under SMS mode this means writing two bytes to it.

However mode 5 has longer commands (24-bit precisely), except for register writes which remain the same. Under MD mode you do this by writing two words in a row. However, mode 5 commands also work in SMS mode, by writing three bytes in a row. This means that you can access all 64KB of VRAM as well as VSRAM, or even read CRAM if you really want.

The odd part is that they seem to have made it explicit. You'd expect it to be two bytes (e.g. not support the longer commands) or four bytes (naively implement two words), but nope, the checks seem to be explicitly designed to reset it as soon as the extra byte is written (regardless of CPU).

VDP status port in mode 5

The status port on the Mega Drive VDP has 10 bits. Normally only the bottom 8 bits are accessible in SMS mode (no big deal since the two missing bits are not present on a Master System VDP anyway)… except under the following contrived conditions:

The VDP must be in mode 5
You must read one of the VDP status port mirrors with address bit 1 clear (e.g. $BD instead of $BF)

When this happens, bits 1-0 of the status port are replaced with bits 9-8, allowing access to all 10 bits. I don't think this is mentioned anywhere (who'd think to try one of the mirrors in a mode that may not have even worked?).

Other stuff...

Again, I'm getting this info by reading verilog code and I haven't been able to verify this myself yet so I may have misunderstood something.

I haven't gotten to the data port yet, so I have no idea how memory accesses work. I imagine that VRAM works as usual but no idea about CRAM or VSRAM (I wouldn't be surprised if it works like CRAM on the Game Gear, however). I also have no idea if DMA transfer works at all.

Whatever the case it does seem like Sega tried hard to ensure mode 5 works in SMS mode, or at least with a Z80. As for why they'd do that? My guess is that they still weren't sure if they'd use a 68000 (from an interview, I can't link since the user account is too recent lol):

Quote

“Yes, the designs for the graphics parts had already begun, and we had an issue regarding the cost, as it was quite a late stage when he had decided on the main CPU would be the 68000 (Motorola 68000 processor),” Ishikawa reminisces. “The reason we used two CPUs was because we believed that the load would be too heavy, had we used one to handle both sound and visuals. Due to that reason, we used the Z-80 as a sub-CPU to handle the sound, which reduced the load on the main CPU while maintaining compatibility.

The link to the interview Sik was talking about by the way.

This is absolutely incredible stuff. I'm really glad you looked into this.

I guess this is the original text: https://web.archive.org/web/20130818192544/https://www.famitsu.com/news/201308/1... but it seems there’s very little 8-bit in there. Maybe we need to interview him about the SG-1000 III and Master System :) It does seem to make it clear that the VDP was made by Yamaha and not under his direct control.

I'm tempted to think they might have done something to make games "dual compatible" (eg: running a game in SMS Mode 4 when on the SMS, Mode 5 when on a Megadrive) and perhaps it didn't pan out?

The only other guess I can wager is for developer familiarity; it likely would have been cheaper for several companies to merely make "dressed up" SMS games and let them use the same old Z80 dev setups and devkits they've been using.

The reason why I don't think it's because of any CPU shenanigans is because the quote reads more like they were simply unsure which architecture to use as the main CPU (I don't see any implications that there wasn't ever going to be a more capable main CPU) and simply settled on making the 68000 the main CPU architecture of choice. In other words, to me it implies that there was always going to be two CPUs, and they weren't sure what the main CPU should be.

Anyways, I find it fascinating that Mode 5 even works in SMS mode at all. I'm doubly impressed that Sega went out of their way to deliberately ensure it worked too, even going the extra mile in places. Combine this with the supposed Z80 overclock (if it even works in SMS mode) and you have a sort of "Super SMS" that isn't quite as powerful as the resulting Megadrive but is much more capable than a stock SMS. It's a bit like the MSX2+ models; the MSX-Engine ASIC can be overclocked (which also alters the PSG clock) and said models also received a visual enhancement as well (V9958 VDP over the V9938). Actually, given that similarity, perhaps we should call the Megadrive equivalent the SMS2+, lol.

Although, is the decap just the YM7101 ASIC? I'm sure the later Megadrive ones (like FC1004) have this as well, but it'd be nice to confirm it's there as well (or really, hardware confirm any of this; I could definitely do some testing in that regard as I have actual consoles).

Author	Message
Sik Joined: 11 Jun 2024 Posts: 2	Mega Drive VDP quirks in SMS mode Posted: Tue Jun 11, 2024 12:37 pm
Sik Joined: 11 Jun 2024 Posts: 2	These last days I've been busy reading the code from nukeykt's Verilog recreation based on the VDP decap trying to figure out how the Mega Drive VDP works and started to notice some oddities regarding SMS mode (especially when trying to use mode 5). Just to make it clear, I haven't been able to verify this myself (I don't have the suitable hardware at hand), so it may be better if somebody here checks this on actual hardware to make sure. In case some users here aren't aware with all these terms as they're largely Mega Drive specific: SMS mode: console is in Master System compatibility mode MD mode: console is in Mega Drive mode Mode 4: VDP is in the Master System graphics mode Mode 5: VDP is in the Mega Drive graphics mode VDP commands in mode 5 Under mode 4, VDP commands are 16-bit. Under MD mode this means writing one word to the control port, while under SMS mode this means writing two bytes to it. However mode 5 has longer commands (24-bit precisely), except for register writes which remain the same. Under MD mode you do this by writing two words in a row. However, mode 5 commands also work in SMS mode, by writing three bytes in a row. This means that you can access all 64KB of VRAM as well as VSRAM, or even read CRAM if you really want. The odd part is that they seem to have made it explicit. You'd expect it to be two bytes (e.g. not support the longer commands) or four bytes (naively implement two words), but nope, the checks seem to be explicitly designed to reset it as soon as the extra byte is written (regardless of CPU). VDP status port in mode 5 The status port on the Mega Drive VDP has 10 bits. Normally only the bottom 8 bits are accessible in SMS mode (no big deal since the two missing bits are not present on a Master System VDP anyway)… except under the following contrived conditions: The VDP must be in mode 5 You must read one of the VDP status port mirrors with address bit 1 clear (e.g. $BD instead of $BF) When this happens, bits 1-0 of the status port are replaced with bits 9-8, allowing access to all 10 bits. I don't think this is mentioned anywhere (who'd think to try one of the mirrors in a mode that may not have even worked?). Other stuff... Again, I'm getting this info by reading verilog code and I haven't been able to verify this myself yet so I may have misunderstood something. I haven't gotten to the data port yet, so I have no idea how memory accesses work. I imagine that VRAM works as usual but no idea about CRAM or VSRAM (I wouldn't be surprised if it works like CRAM on the Game Gear, however). I also have no idea if DMA transfer works at all. Whatever the case it does seem like Sega tried hard to ensure mode 5 works in SMS mode, or at least with a Z80. As for why they'd do that? My guess is that they still weren't sure if they'd use a 68000 (from an interview, I can't link since the user account is too recent lol): Quote “Yes, the designs for the graphics parts had already begun, and we had an issue regarding the cost, as it was quite a late stage when he had decided on the main CPU would be the 68000 (Motorola 68000 processor),” Ishikawa reminisces. “The reason we used two CPUs was because we believed that the load would be too heavy, had we used one to handle both sound and visuals. Due to that reason, we used the Z-80 as a sub-CPU to handle the sound, which reduced the load on the main CPU while maintaining compatibility.

Flygon Joined: 30 Jun 2016 Posts: 197 Location: Australia	Posted: Tue Jun 11, 2024 10:11 pm
	The link to the interview Sik was talking about by the way. This is absolutely incredible stuff. I'm really glad you looked into this.

Maxim Site Admin Joined: 19 Oct 1999 Posts: 14769 Location: London	Posted: Tue Jun 11, 2024 11:26 pm
	I guess this is the original text: https://web.archive.org/web/20130818192544/https://www.famitsu.com/news/201308/1... but it seems there’s very little 8-bit in there. Maybe we need to interview him about the SG-1000 III and Master System :) It does seem to make it clear that the VDP was made by Yamaha and not under his direct control.

forple Joined: 14 Jan 2023 Posts: 1 Location: United States	Posted: Wed Jun 12, 2024 4:54 am
	I'm tempted to think they might have done something to make games "dual compatible" (eg: running a game in SMS Mode 4 when on the SMS, Mode 5 when on a Megadrive) and perhaps it didn't pan out? The only other guess I can wager is for developer familiarity; it likely would have been cheaper for several companies to merely make "dressed up" SMS games and let them use the same old Z80 dev setups and devkits they've been using. The reason why I don't think it's because of any CPU shenanigans is because the quote reads more like they were simply unsure which architecture to use as the main CPU (I don't see any implications that there wasn't ever going to be a more capable main CPU) and simply settled on making the 68000 the main CPU architecture of choice. In other words, to me it implies that there was always going to be two CPUs, and they weren't sure what the main CPU should be. Anyways, I find it fascinating that Mode 5 even works in SMS mode at all. I'm doubly impressed that Sega went out of their way to deliberately ensure it worked too, even going the extra mile in places. Combine this with the supposed Z80 overclock (if it even works in SMS mode) and you have a sort of "Super SMS" that isn't quite as powerful as the resulting Megadrive but is much more capable than a stock SMS. It's a bit like the MSX2+ models; the MSX-Engine ASIC can be overclocked (which also alters the PSG clock) and said models also received a visual enhancement as well (V9958 VDP over the V9938). Actually, given that similarity, perhaps we should call the Megadrive equivalent the SMS2+, lol. Although, is the decap just the YM7101 ASIC? I'm sure the later Megadrive ones (like FC1004) have this as well, but it'd be nice to confirm it's there as well (or really, hardware confirm any of this; I could definitely do some testing in that regard as I have actual consoles).

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