The following has been adapted from an abbreviated summary of the Z80 instruction set, originally written by Devin Gardner (Cepaughfe AT on 2000.04.29 for (Find the original at Reproduced without permission.

Check the end of the list for explanations of abbreviations used below.

ADC A,r41***V0*88+rAdd with CarryA=A+s+CY
ADC A,(HL)71 8E  
ADC A,(IX+d)193 DD 8E XX  
ADC A,(IY+d)193 FD 8E XX  
ADC HL,BC152**?V0*ED 4AAdd with CarryHL=HL+ss+CY
ADC HL,DE152 ED 5A  
ADC HL,HL152 ED 6A  
ADC HL,SP152 ED 7A  
ADD A,r41***V0*80+rAdd (8-bit)A=A+s
ADD A,N72 C6 XX  
ADD A,(HL)71 86  
ADD A,(IX+d)193 DD 86 XX  
ADD A,(IY+d)193 FD 86 XX  
ADD HL,BC111--?-0*09Add (16-bit)HL=HL+ss
ADD HL,DE111 19  
ADD HL,HL111 29  
ADD HL,SP111 39  
ADD IX,BC152--?-0*DD 09Add (IX register)IX=IX+pp
ADD IX,DE152 DD 19  
ADD IX,IX152 DD 29  
ADD IX,SP152 DD 39  
ADD IY,BC152--?-0*FD 09Add (IY register)IY=IY+rr
ADD IY,DE152 FD 19  
ADD IY,IY152 FD 29  
ADD IY,SP152 FD 39  
AND r41***P00A0+rLogical ANDA=A&s
AND N72 E6 XX  
AND (HL)71 A6  
AND (IX+d)193 DD A6 XX  
AND (IY+d)193 FD A6 XX  
BIT b,r82?*1?0-CB 40+8*b+rTest Bitm&{2^b}
BIT b,(HL)122 CB 46+8*b  
BIT b,(IX+d)204 DD CB XX 46+8*b  
BIT b,(IY+d)204 FD CB XX 46+8*b  
CALL NN173------CD XX XXUnconditional Call-(SP)=PC,PC=nn
CALL C,NN17/103------DC XX XXConditional CallIf Carry = 1
CALL NC,NN17/103 D4 XX XX If carry = 0
CALL M,NN17/103 FC XX XX If Sign = 1 (negative)
CALL P,NN17/103 F4 XX XX If Sign = 0 (positive)
CALL Z,NN17/103 CC XX XX If Zero = 1 (ans.=0)
CALL NZ,NN17/103 C4 XX XX If Zero = 0 (non-zero)
CALL PE,NN17/103 EC XX XX If Parity = 1 (even)
CALL PO,NN17/103 E4 XX XX If Parity = 0 (odd)
CCF41--?-0*3FComplement Carry FlagCY=~CY
CP r41***V1*B8+rCompareCompare A-s
CP N72 FE XX  
CP (HL)71 BE  
CP (IX+d)193 DD BE XX  
CP (IY+d)193 FD BE XX  
CPD162****1-ED A9Compare and DecrementA-(HL),HL=HL-1,BC=BC-1
CPDR21/162****1-ED B9Compare, Decrement, RepeatCPD till A=(HL)or BC=0
CPI162****1-ED A1Compare and IncrementA-(HL),HL=HL+1,BC=BC-1
CPIR21/162****1-ED B1Compare, Increment, RepeatCPI till A=(HL)or BC=0
DAA41***P-*27Decimal Adjust AccumulatorA=BCD format (dec.)
DEC A41***V1-3DDecrement (8-bit)s=s-1
DEC B41 05  
DEC C41 0D  
DEC D41 15  
DEC E41 1D  
DEC H41 25  
DEC L42 2D  
DEC (HL)111 35  
DEC (IX+d)233 DD 35 XX  
DEC (IY+d)233 FD 35 XX  
DEC BC61------0BDecrement (16-bit)ss=ss-1
DEC DE61 1B  
DEC HL61 2B  
DEC SP61 3B  
DEC IX102------DD 2BDecrementxx=xx-1
DEC IY102 FD 2B  
DI41------F3Disable Interrupts 
DJNZ $+213/82------10 XXDecrement, Jump if Non-ZeroB=B-1 till B=0
EI41------FBEnable Interrupts 
EX (SP),HL191------E3Exchange(SP)<->HL
EX (SP),IX232------DD E3 (SP)<->xx
EX (SP),IY232 FD E3  
EX AF,AF'41------08 AF<->AF'
EX DE,HL41------EB DE<->HL
EXX41------D9Exchangeqq<->qq' (except AF)
IM 082------ED 46Interrupt Mode(n=0,1,2)
IM 182 ED 56  
IM 282 ED 5E  
IN A,(N)112------DB XXInputA=(n)
IN (C)122***P0-ED 70Input*Unsupported
IN A,(C)122***P0-ED 78Inputr=(C)
IN B,(C)122 ED 40  
IN C,(C)122 ED 48  
IN D,(C)122 ED 50  
IN E,(C)122 ED 58  
IN H,(C)122 ED 60  
IN L,(C)122 ED 68  
INC A41***V0-3CIncrement (8-bit)r=r+1
INC B41 04  
INC C41 0C  
INC D41 14  
INC E41 1C  
INC H41 24  
INC L41 2C  
INC BC61------03Increment (16-bit)ss=ss+1
INC DE61 13  
INC HL61 23  
INC SP61 33  
INC IX102------DD 23Incrementxx=xx+1
INC IY102 FD 23  
INC (HL)111***V0-34Increment (indirect)(HL)=(HL)+1
INC (IX+d)233***V0-DD 34 XXIncrement(xx+d)=(xx+d)+1
INC (IY+d)233 FD 34 XX  
IND162?*??1*ED AAInput and Decrement(HL)=(C),HL=HL-1,B=B-1
INDR21/162?1??1*ED BAInput, Decrement, RepeatIND till B=0
INI162?*??1*ED A2Input and Increment(HL)=(C),HL=HL+1,B=B-1
INIR21/162?1??1*ED B2Input, Increment, RepeatINI till B=0
JP $NN103------C3 XX XXUnconditional JumpPC=nn
JP (HL)41------E9Unconditional JumpPC=HL
JP (IX)82------DD E9Unconditional JumpPC=xx
JP (IY)82 FD E9  
JP C,$NN103------DA XX XXConditional JumpIf Carry = 1
JP NC,$NN103 D2 XX XX If Carry = 0
JP M,$NN103 FA XX XX If Sign = 1 (negative)
JP P,$NN103 F2 XX XX If Sign = 0 (positive)
JP Z,$NN103 CA XX XX If Zero = 1 (ans.= 0)
JP NZ,$NN103 C2 XX XX If Zero = 0 (non-zero)
JP PE,$NN103 EA XX XX If Parity = 1 (even)
JP PO,$NN103 E2 XX XX If Parity = 0 (odd)
JR $N+2122------18 XXRelative JumpPC=PC+e
JR C,$N+212/72------38 XXCond. Relative JumpIf cc JR(cc=C,NC,NZ,Z)
JR NC,$N+212/72 30 XX  
JR Z,$N+212/72 28 XX  
JR NZ,$N+212/72 20 XX  
LD I,A92------ED 47Load*dst=src
LD R,A92 ED 4F  
LD A,I92**0*0-ED 57Load*dst=src
LD A,R92 ED 5F  
LD A,r41------78+rLoad (8-bit)dst=src
LD A,N72 3E XX  
LD A,(BC)71 0A  
LD A,(DE)71 1A  
LD A,(HL)71 7E  
LD A,(IX+d)193 DD 7E XX  
LD A,(IY+d)193 FD 7E XX  
LD A,(NN)133 3A XX XX  
LD B,r41 40+r  
LD B,N72 06 XX  
LD B,(HL)71 46  
LD B,(IX+d)193 DD 46 XX  
LD B,(IY+d)193 FD 46 XX  
LD C,r41 48+r  
LD C,N72 0E XX  
LD C,(HL)71 4E  
LD C,(IX+d)193 DD 4E XX  
LD C,(IY+d)193 FD 4E XX  
LD D,r41 50+r  
LD D,N72 16 XX  
LD D,(HL)71 56  
LD D,(IX+d)193 DD 56 XX  
LD D,(IY+d)193 FD 56 XX  
LD E,r41 58+r  
LD E,N72 1E XX  
LD E,(HL)71 5E  
LD E,(IX+d)193 DD 5E XX  
LD E,(IY+d)193 FD 5E XX  
LD H,r41 60+r  
LD H,N72 26 XX  
LD H,(HL)71 66  
LD H,(IX+d)193 DD 66 XX  
LD H,(IY+d)193 FD 66 XX  
LD L,r41 68+r  
LD L,N72 2E XX  
LD L,(HL)71 6E  
LD L,(IX+d)193 DD 6E XX  
LD L,(IY+d)193 FD 6E XX  
LD BC,(NN)204------ED 4B XX XXLoad (16-bit)dst=src
LD BC,NN103 01 XX XX  
LD DE,(NN)204 ED 5B XX XX  
LD DE,NN103 11 XX XX  
LD HL,(NN)163 2A XX XX  
LD HL,NN103 21 XX XX  
LD SP,(NN)204 ED 7B XX XX  
LD SP,HL61 F9  
LD SP,IX102 DD F9  
LD SP,IY102 FD F9  
LD SP,NN103 31 XX XX  
LD IX,(NN)204 DD 2A XX XX  
LD IX,NN144 DD 21 XX XX  
LD IY,(NN)204 FD 2A XX XX  
LD IY,NN144 FD 21 XX XX  
LD (HL),r71------70+rLoad (Indirect)dst=src
LD (HL),N102 36 XX  
LD (BC),A71 02  
LD (DE),A71 12  
LD (NN),A133 32 XX XX  
LD (NN),BC204 ED 43 XX XX  
LD (NN),DE204 ED 53 XX XX  
LD (NN),HL163 22 XX XX  
LD (NN),IX204 DD 22 XX XX  
LD (NN),IY204 FD 22 XX XX  
LD (NN),SP204 ED 73 XX XX  
LD (IX+d),r193 DD 70+r XX  
LD (IX+d),N194 DD 36 XX XX  
LD (IY+d),r193 FD 70+r XX  
LD (IY+d),N194 FD 36 XX XX  
LDD162--0*0-ED A8Load and Decrement(DE)=(HL), HL=HL-1, BC=BC-1, DE=DE-1
LDDR21/162--000-ED B8Load, Decrement, RepeatLDD until BC=0
LDI162--0*0-ED A0Load and Increment(DE)=(HL), HL=HL+1, BC=BC-1, DE=DE+1
LDIR21/162--000-ED B0Load, Increment, RepeatLDI until BC=0
NEG82***V1*ED 44NegateA=-A
NOP41------00No Operation 
OR r41***P00B0+rLogical inclusive ORA=Avs
OR N72 F6 XX  
OR (HL)71 B6  
OR (IX+d)193 DD B6 XX  
OR (IY+d)193 FD B6 XX  
OUT (N),A112------D3 XXOutput(n)=A
OUT (C),0122------ED 71Output*Unsupported
OUT (C),A122------ED 79Output(C)=r
OUT (C),B122 ED 41  
OUT (C),C122 ED 49  
OUT (C),D122 ED 51  
OUT (C),E122 ED 59  
OUT (C),H122 ED 61  
OUT (C),L122 ED 69  
OUTD162?*??1*ED ABOutput and Decrement(C)=(HL),HL=HL-1,B=B-1
OTDR21/162?1??1*ED BBOutput, Decrement, RepeatOUTD until B=0
OUTI162?*??1*ED A3Output and Increment(C)=(HL),HL=HL+1,B=B-1
OTIR21/162?1??1*ED B3Output, Increment, RepeatOUTI until B=0
POP AF101------F1Popqq=(SP)+
POP BC101 C1  
POP DE101 D1  
POP HL101 E1  
POP IX142------DD E1Popxx=(SP)+
POP IY142 FD E1  
PUSH AF111------F5Push-(SP)=qq
PUSH BC111 C5  
PUSH DE111 D5  
PUSH HL111 E5  
PUSH IX152------DD E5Push-(SP)=xx
PUSH IY152 FD E5  
RES b,r82------CB 80+8*b+rReset bitm=m&{~2^b}
RES b,(HL)152------CB 86+8*b  
RES b,(IX+d)234------DD CB XX 86+8*b  
RES b,(IY+d)234------FD CB XX 86+8*b  
RET C11/51------D8Conditional ReturnIf Carry = 1
RET NC11/51 D0 If Carry = 0
RET M11/51 F8 If Sign = 1 (negative)
RET P11/51 F0 If Sign = 0 (positive)
RET Z11/51 C8 If Zero = 1 (ans.=0)
RET NZ11/51 C0 If Zero = 0 (non-zero)
RET PE11/51 E8 If Parity = 1 (even)
RET PO11/51 E0 If Parity = 0 (odd)
RETI142------ED 4DReturn from InterruptPC=(SP)+
RETN142------ED 45Return from NMIPC=(SP)+
RLA41--0-0*17Rotate Left AccumulatorA={CY,A}<-
RL r82**0P0*CB 10+rRotate Leftm={CY,m}<-
RL (HL)152 CB 16  
RL (IX+d)234 DD CB XX 16  
RL (IY+d)234 FD CB XX 16  
RLCA41--0-0*07Rotate Left Circular AccumulatorA=A<-
RLC r82**0P0*CB 00+rRotate Left Circularm=m<-
RLC (HL)152 CB 06  
RLC (IX+d)234 DD CB XX 06  
RLC (IY+d)234 FD CB XX 06  
RLD182**0P0-ED 6FRotate Left 4 bits{A,(HL)}={A,(HL)}<- (Only lower 4 bits of accumulator A used)
RRA41--0-0*1FRotate Right AccumulatorA=->{CY,A}
RR r82**0P0*CB 18+rRotate Rightm=->{CY,m}
RR (HL)152 CB 1E  
RR (IX+d)234 DD CB XX 1E  
RR (IY+d)234 FD CB XX 1E  
RRCA41--0-0*0FRotate Right Circular AccumulatorA=->A
RRC r82**0P0*CB 08+rRotate Right Circularm=->m
RRC (HL)152 CB 0E  
RRC (IX+d)234 DD CB XX 0E  
RRC (IY+d)234 FD CB XX 0E  
RRD182**0P0-ED 67Rotate Right 4 bits{A,(HL)}=->{A,(HL)} (Only lower 4 bits of accumulator A used)
RST 0111------C7Restart(p=0H,8H,10H,...,38H)
RST 08H111 CF  
RST 10H111 D7  
RST 18H111 DF  
RST 20H111 E7  
RST 28H111 EF  
RST 30H111 F7  
RST 38H111 FF  
SBC r41***V1*98+rSubtract with CarryA=A-s-CY
SBC (HL)71 9E  
SBC A,(IX+d)193 DD 9E XX  
SBC A,(IY+d)193 FD 9E XX  
SBC HL,BC152**?V1*ED 42Subtract with CarryHL=HL-ss-CY
SBC HL,DE152 ED 52  
SBC HL,HL152 ED 62  
SBC HL,SP152 ED 72  
SCF41--0-0137Set Carry FlagCY=1
SET b,r82------CB C0+8*b+rSet bitm=mv{2^b}
SET b,(HL)152 CB C6+8*b  
SET b,(IX+d)234 DD CB XX C6+8*b  
SET b,(IY+d)234 FD CB XX C6+8*b  
SLA r82**0P0*CB 20+rShift Left Arithmeticm=m*2
SLA (HL)152 CB 26  
SLA (IX+d)234 DD CB XX 26  
SLA (IY+d)234 FD CB XX 26  
SRA r82**0P0*CB 28+rShift Right Arithmeticm=m/2 (previous content of bit 7 is unchanged)
SRA (HL)152 CB 2E  
SRA (IX+d)234 DD CB XX 2E  
SRA (IY+d)234 FD CB XX 2E  
SLL r82**0P0*CB 30+rShift Left Logical*m={0,m,CY}<-
SLL (HL)152 CB 36 (SLL instructions are Unsupported)
SLL (IX+d)234 DD CB XX 36  
SLL (IY+d)234 FD CB XX 36  
SRL r82**0P0*CB 38+rShift Right Logicalm=->{0,m,CY}
SRL (HL)152 CB 3E  
SRL (IX+d)234 DD CB XX 3E  
SRL (IY+d)234 FD CB XX 3E  
SUB r41***V1*90+rSubtractA=A-s
SUB N72 D6 XX  
SUB (HL)71 96  
SUB (IX+d)193 DD 96 XX  
SUB (IY+d)193 FD 96 XX  
XOR r41***P00A8+rLogical Exclusive ORA=Axs
XOR (HL)71 AE  
XOR (IX+d)193 DD AE XX  
XOR (IY+d)193 FD AE XX  

* Unsupported instruction: Use the hexadecimal OP-Codes with the assembler instruction ".db" For example, instead of "SLL (HL)", use ".db $CB,$36"

SZHPNC = How the different bits of the Flag byte (the F in the AF register) are affected. Check the FLAGS table below this for more.

Op-code = The instruction's equivalent in hexadecimal.

"r" means register. It can be A,B,C,D,E,H, or L. Add this to last byte of OP-code:


In "LD (IX+d),r" and "LD (IY+d),r" you add these to the byte BEFORE the last.

"b" means bit. It can be 0-7. Increase the last byte of the OP-code with 8 times b. Used in SET, BIT and RES.

If there are two numbers given for Cycles, then the highest is when the jump is taken, the lowest is when it skips the jump.


-*01?Flag unaffected/affected/reset/set/unknown
SSign flag (Bit 7)
ZZero flag (Bit 6)
HCHalf Carry flag (Bit 4)
P/ VParity/Overflow flag (Bit 2, V=overflow)
NAdd/Subtract flag (Bit 1)
CYCarry flag (Bit 0)


nImmediate addressing
nnImmediate extended addressing
eRelative addressing (PC=PC+2+offset)
(nn)Extended addressing
(xx+d)Indexed addressing
rRegister addressing
(rr)Register indirect addressing
 Implied addressing
bBit addressing
pModified page zero addressing (see RST)


A B C D ERegisters (8-bit)
AF BC DE HLRegister pairs (16-bit)
FFlag register (8-bit)
IInterrupt page address register (8-bit)
IX IYIndex registers (16-bit)
PCProgram Counter register (16-bit)
RMemory Refresh register
SPStack Pointer register (16-bit)


bOne bit (0 to 7)
ccCondition (C,M,NC,NZ,P,PE,PO,Z)
dOne-byte expression (-128 to +127)
dstDestination s, ss, (BC), (DE), (HL), (nn)
eOne-byte expression (-126 to +129)
mAny register r, (HL) or (xx+d)
nOne-byte expression (0 to 255)
nnTwo-byte expression (0 to 65535)
ppRegister pair BC, DE, IX or SP
qqRegister pair AF, BC, DE or HL
qq'Alternative register pair AF, BC, DE or HL
rRegister A, B, C, D, E, H or L
rrRegister pair BC, DE, IY or SP
sAny register r, value n, (HL) or (xx+d)
srcSource s, ss, (BC), (DE), (HL), nn, (nn)
ssRegister pair BC, DE, HL or SP
xxIndex register IX or IY


+ - * / ^Add/subtract/multiply/divide/exponent
& ~ v xLogical AND/NOT/inclusive OR/exclusive OR
<- ->Rotate left/right
( )Indirect addressing
( )+ -( )Indirect addressing auto-increment/decrement
{ }Combination of operands

Return to top