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View topic - CPLD Paging IC (mapper)

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  • Joined: 24 Sep 2006
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CPLD Paging IC (mapper)
Post Posted: Sun Mar 25, 2007 12:33 pm
I was working on a fancy kind of Megadrive/Master System flash cartridge a couple of months ago but have since lost interest in the project (like so many others...). One part I did actually finish is the Master System paging IC, implemented in an Altera CPLD. It's meant to be compatible will all commercial games (I didn't bother including all the strange little features of the sega chips that nobody actually made use of). So here it is...in case somebody is interested.

http://members.optusnet.com.au/eviltim/smsmap/

The design was entered through a schematic capture but unfortunately, the software doesn't allow exporting the schematic as an image. I've had to resort to the old "print and scan" method to get these images.

There is also a photo of the prototype I built to test it. The paging circuit consists of two ICs and a jumper. The first IC is the CPLD, an EPM7064. The design is just slightly too big to fit into a smaller EPM7032 as is, but will fit if the FF_0 is removed (this breakes at least one game). The second IC is a 74LS30 - 8 input NAND gate, which helps with the address decoding (A2-A9). The jumper is connected to the SEGA pin. Pull pin high = Sega mode, pull pin low = Codemasters mode.

As I stated above, the idea was to support EVERY SINGLE GAME. So that means support for up to 8Mbit of rom, 32k (both pages) of SRAM, and compatible with both Sega and Codemasters paging techniques. I have so far only tested about 10 different games...no a large sample but I think there is variation beetween the games I selected to test everything. Due to the limitations of my prototype (it has a socket for only a 4Mbit flash chip) and my Master system (it has a BIOS), I couldn't check 8Mbit and/or Korean/Japanese games.
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Post Posted: Sun Mar 25, 2007 1:37 pm
You can fix up the headers on most Japanese games easily enough (well, there is no automatic tool to do it to avoid having altered roms floating around but it's a few seconds' work in a hex editor).

As for "print and scan", you could try getting one of those (free) virtual printer PDF programs. I think there are some that can output bitmaps too; or the even more old-fashioned way is to get a big screen and stitch together some screen captures.
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  • Joined: 20 Feb 2007
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Post Posted: Sun Mar 25, 2007 9:10 pm
Is there something wrong with the link? all i can see is a YouTube picture coming soon pic.
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  • Joined: 10 May 2005
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Post Posted: Sun Mar 25, 2007 9:50 pm
paul_ wrote
Is there something wrong with the link? all i can see is a YouTube picture coming soon pic.


Nope, it works fine for me - as do all the images.
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Post Posted: Mon Mar 26, 2007 2:05 am
Ah cool, works now for me too.
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Post Posted: Fri Apr 22, 2011 5:43 pm
viletim,
after many years I bring that topic back to the top.

Nice work, I can´t find the logic files for download.
have you ever published them?

Did you use the "S" Type of the EPM7064?
If not, how have you programmed it?

Which software did you use to desingn?

I
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Post Posted: Fri Apr 22, 2011 8:44 pm
He's used the EPM7064SLC44-10 I believe.
Here's a link to a RoHS compliant EPM7064SLC44-10N http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=544-2012-ND
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Post Posted: Mon Apr 25, 2011 10:11 am
django,

Here is the software, Altera Max Plus II, with an unrestricted licence file. The pdf file contains the circuit for the programming cable I was using, the zip contains the project files.

http://etim.net.au/temp/maxplus10.2/
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Post Posted: Thu Apr 28, 2011 6:29 pm
thanks, I´ll try it if I get a chip.
you can get the non-S(erial(JTAG)) Types really cheap, but noone in the whole
Internet know how to program them - have googeled for hours.

Did you know wich chips from Atmel match the requirements?
that´s why I asked for the pof2jed tool which converts the pov file
for use with atmel chips.
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Post Posted: Fri Apr 29, 2011 12:10 pm
django wrote
thanks, I´ll try it if I get a chip.
you can get the non-S(erial(JTAG)) Types really cheap, but noone in the whole
Internet know how to program them - have googeled for hours.


PLDs from the pre-internet days with secret proprietary programming algorithms... I can see why they're cheap! Better buy the JTAG ones instead.

django wrote

Did you know wich chips from Atmel match the requirements?
that´s why I asked for the pof2jed tool which converts the pov file
for use with atmel chips.


I don't think that's going to work. CPLDs from different manufacturers are not compatible with one another. You can't pick and choose development tools or even hardware description methods sometimes. I only have experience with Altera and Xilinx. They both offer a simple HDL (AHDL, CUPL, etc), a frighteningly complex HDL (VHDL, Verilog, etc), and schematic capture.

I like to use Altera parts because their MAX II software has schematic capture input that works fairly well. I prefer to express logic in diagram form, as the HDLs are a bit cryptic and therefore slower to create. Instead of picking the part first, I find its best to design the logic first and then synthesize and see which devices it will fit.

If you're dead set on an Atmel part, it looks like you will have to make friends with CUPL.
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Post Posted: Mon Dec 31, 2018 5:26 am
I built a copy of this, and so far it seems to be working, although I have only tried one game so far and not yet tested the backup RAM.


I wanted to ask a question about Max+plus though, for using your design, I simply wrote the smsmap_full POF file to a EPM7064SLC without issue, but if I try to compile the project from scratch, it says it won't even fit in the device - yet you obviously managed it somehow. What am I missing?

I ask because I'm trying to emulate the other mapper circuit, that was based on the 7400 series ICs, but it won't fit either - despite having a much simpler design.


EDIT: never mind, I had EPM7032SLC selected by accident, so of course it didn't fit.
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