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SDSC Document Template
Introduction
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About this Document
This document is a template that can be used for the creation of SDSC documents. It is intended only as a starting point. Adjust the Table of Contents and the chapters as appropriate. Also, remove this paragraph and replace with the actual introduction paragraph.
Document Conventions
This document uses a specific notation for hexadecimal and binary numbers, symbolic representation of instructions, and data-structure formats. Familiarity with this notation is essential to understanding this document.
Hexadecimal and Binary Numbers
Hexadecimal (Base 16) numbers are represented using the WLA-DX format of the "$" symbol followed by a string of hexadecimal digits (1-9 and A-F). The hexadecimal digits 'A' through 'F' will always be upper-case. A valid hexadecimal number representation would be: $C0FF.
Binary (Base 2) numbers are represented using the WLA-DX format of the "%" symbol followed by a string of binary digits (0 and 1). A valid binary number representation would be: %11100110.
Bit and Byte Order
Bits are numbered starting from right to left, (i.e., least-significant to most-significant.) All bytes consist of eight bits: 0 through 7.
The SMS and GG machines are both based on Zilog's Z80 microprocessor. This microprocessor is a "little-endian" machine, meaning that bytes of a word are numbered starting from the least-significant byte. As a result, the SMS and GG machines are also little-endian. The least-significant byte in a word will always be stored to memory first, at the lower address, followed by the most-significant byte at the higher address.
Diagrams of data structures in memory will have lower memory addresses towards the bottom of the page, with higher addresses growing towards the top of the page.
Reserved Bits
In certain register layout descriptions, various bits will be marked as "Reserved." All reserved bits are implicitly RESET (0). Software should never attempt to SET these bits (to 1). Follow the guidelines below:
- Do not depend on the states of any reserved bits when testing the values of defined register bits. Mask out the reserved bits when testing.
- Do not depend on the states of any reserved bits when storing them to memory or another register.
- Do not depend on the ability to retain information written into any reserved bits.
- Always load the reserved bits as zeros.
Instruction Operands
The main processor used in the SMS and GG machines is the Zilog Z80 microprocessor. The symbolic representation of instructions is taken directly from Z80 assembly language. The format is shown below:
label: mnemonic argument1, argument2
where:
- A label is an identifier followed by a colon (:).
- A mnemonic is a reserved name for a class of instruction opcodes which have the same function.
- The operands argument1, argument2 are optional. There may be zero, one, or two arguments, depending on the instruction. When present, they are either literals, or data identifiers. The data identifiers are either reserved register names, or are assigned to data items declared elsewhere in the source file.
When two operands are present, the right operand is the source and the left is the destination.
For example:
In this example, LOOP1 is a label, LD is the mnemonic identifier for the opcode, HL is the destination operand, and STARTVALUE is the source operand.
Revision History
Version ?.?? (Month Date, Year): Comment.
I.4 Acknowledgements
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Chapter ?: Put Chapter Title Here
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