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I've updated the Paging Chips document to include new information about the 315-5365. I've also updated the pin-outs of all three known paging chips. I'm hoping those familiar with these chips will take a brief look at the pin-outs to confrim that everything is correct.

I've also moved the document to the "Memory" section of the docs page.

--
Eric Quinn

Quote

> I've updated the Paging Chips document to include new information about the 315-5365. I've also updated the pin-outs of all three known paging chips. I'm hoping those familiar with these chips will take a brief look at the pin-outs to confrim that everything is correct.

You forgot to update 'Revision'.
Also, Casino Games board is brown.

Thanks, Eric.

Quote

> I've updated the Paging Chips document to include new information about the 315-5365. I've also updated the pin-outs of all three known paging chips. I'm hoping those familiar with these chips will take a brief look at the pin-outs to confrim that everything is correct.

OK, good work! Just a few additions:

1) The _M0-7 (a.k.a. _EXM2) pin of the 315-5208 is a control input, not an output.

2) Pin 31 of the 315-5235 is _WR IN (not out).

3) I believe (though I haven't confirmed it 100% yet) that pins 25, 15, 16 and 17 of the 315-5235 correspond to pins 25, 14, 15 and 16 respectively of the 315-5365, and behave in the same way. I will test it out and let you know if this is the case.

Mike

on the topic of /CE ouput lines from the 5235,

it appears that under these 'pin 25 config's' that the memory space is limited to 512kB/0x7FFFF allowing for ROM combinations of 1 x 512k, 2 x 256k and 2 x 128k + 256k. the number of input address lines (D0 to D4) also limit the memory space to 32 x 16kB segments, 512kB.

but there are still a few untested variables like the D7 input. does each register also include a D7 bit and would this allow for 2 banks of 512kB (2 x 32 x 16kB) controlled by the CE lines?

what are the functions of the other bits (D0, D1, D2, D7) of register FFFC, the register that controls SRAM. perhaps this registers provides software control over ROM banking and paging, similar to IO port 3E. and speaking of SRAM paging, is there an output that controls A14 of SRAM? maybe its the NC pin...

and finally, it could also be possible that pins 27 and possibly 28 also configure the operation of the CE ouputs.

a pondering A S out.

Author	Message
Eric R. Quinn Joined: 18 Sep 1999 Posts: 498 Location: Portland, Oregon USA	Paging Chips Update Posted: Sun Jan 20, 2002 8:31 pm
	All- I've updated the Paging Chips document to include new information about the 315-5365. I've also updated the pin-outs of all three known paging chips. I'm hoping those familiar with these chips will take a brief look at the pin-outs to confrim that everything is correct. I've also moved the document to the "Memory" section of the docs page. -- Eric Quinn

Bock Site Admin Joined: 08 Jul 2001 Posts: 8653 Location: Paris, France	Nitpicking Posted: Sun Jan 20, 2002 10:09 pm
	Quote > I've updated the Paging Chips document to include new information about the 315-5365. I've also updated the pin-outs of all three known paging chips. I'm hoping those familiar with these chips will take a brief look at the pin-outs to confrim that everything is correct. You forgot to update 'Revision'. Also, Casino Games board is brown. Thanks, Eric.

Mike G Joined: 21 Apr 2000 Posts: 598 Location: Newcastle upon Tyne, England	More nitpicking (not really ;-) ) Posted: Mon Jan 21, 2002 11:39 am
	Quote > I've updated the Paging Chips document to include new information about the 315-5365. I've also updated the pin-outs of all three known paging chips. I'm hoping those familiar with these chips will take a brief look at the pin-outs to confrim that everything is correct. OK, good work! Just a few additions: 1) The _M0-7 (a.k.a. _EXM2) pin of the 315-5208 is a control input, not an output. 2) Pin 31 of the 315-5235 is _WR IN (not out). 3) I believe (though I haven't confirmed it 100% yet) that pins 25, 15, 16 and 17 of the 315-5235 correspond to pins 25, 14, 15 and 16 respectively of the 315-5365, and behave in the same way. I will test it out and let you know if this is the case. Mike

asynchronous Joined: 14 Aug 2000 Posts: 742 Location: Adelaide, Australia	Posted: Tue Jan 22, 2002 4:08 am
	on the topic of /CE ouput lines from the 5235, it appears that under these 'pin 25 config's' that the memory space is limited to 512kB/0x7FFFF allowing for ROM combinations of 1 x 512k, 2 x 256k and 2 x 128k + 256k. the number of input address lines (D0 to D4) also limit the memory space to 32 x 16kB segments, 512kB. but there are still a few untested variables like the D7 input. does each register also include a D7 bit and would this allow for 2 banks of 512kB (2 x 32 x 16kB) controlled by the CE lines? what are the functions of the other bits (D0, D1, D2, D7) of register FFFC, the register that controls SRAM. perhaps this registers provides software control over ROM banking and paging, similar to IO port 3E. and speaking of SRAM paging, is there an output that controls A14 of SRAM? maybe its the NC pin... and finally, it could also be possible that pins 27 and possibly 28 also configure the operation of the CE ouputs. a pondering A S out.

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