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A progress report on the SRAM situation...

I've been trying to figure out ways of configuring a 315-5235 with a battery backed 62256 SRAM chip (instead of a 6264).

As Vic_Viper explained in a previous post, the 62256 is tricky to use because it only has one chip enable pin. The 6264 has a second, inverted CE pin, which can be connected to the battery watchdog circuit in order to put the SRAM into standby mode when the console is turned off.

Here is one method I tried but which failed to work. The SRAM can be written and read using my cartridge reader, but the ROM cannot be read correctly (corrupt data). It gives a "SOFTWARE ERROR" when plugged into the SMS.

The OR gate is implemented using a 4011 quad CMOS NAND gate.

(The watchdog chip, by the way, is a Harris 7673, which I think I mentioned before. Here's the data sheet for it.)

Here are two more possibilities I thought of (but haven't tested yet):

I'd appreciate any comments. In particular, is there any problem with having the SRAM chip "enabled" all of the time, so long as the _OE and _WR pins are handled correctly?

Another approach I considered was to use the watchdog circuit to power the CMOS 4011 chip, which would allow the configuration shown here:

but maybe there are problems inherent in this? I'm not sure.

Mike

Author	Message
Mike G Joined: 21 Apr 2000 Posts: 598 Location: Newcastle upon Tyne, England	Battery backed SRAM issues Posted: Wed Sep 27, 2000 8:33 pm
	A progress report on the SRAM situation... I've been trying to figure out ways of configuring a 315-5235 with a battery backed 62256 SRAM chip (instead of a 6264). As Vic_Viper explained in a previous post, the 62256 is tricky to use because it only has one chip enable pin. The 6264 has a second, inverted CE pin, which can be connected to the battery watchdog circuit in order to put the SRAM into standby mode when the console is turned off. Here is one method I tried but which failed to work. The SRAM can be written and read using my cartridge reader, but the ROM cannot be read correctly (corrupt data). It gives a "SOFTWARE ERROR" when plugged into the SMS. The OR gate is implemented using a 4011 quad CMOS NAND gate. (The watchdog chip, by the way, is a Harris 7673, which I think I mentioned before. Here's the data sheet for it.) Here are two more possibilities I thought of (but haven't tested yet): I'd appreciate any comments. In particular, is there any problem with having the SRAM chip "enabled" all of the time, so long as the _OE and _WR pins are handled correctly? Another approach I considered was to use the watchdog circuit to power the CMOS 4011 chip, which would allow the configuration shown here: but maybe there are problems inherent in this? I'm not sure. Mike

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