- Joined: 12 Jul 2005
- Posts: 55
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SMS homemade ROM mapper- block 2 picture. The FRAME/PAGE translation block
 Posted: Tue Sep 05, 2000 2:58 am
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This block consists of two 8 bit registers mapped in FFFE (U6 and U12A) and FFFF (U7 and U12B). It's designed to
hold the following values after the power on/hardware reset cycle:
FFFE - will output 00000001 to the FRAME/PAGE translation logic
FFFF - will output 00000010 to the FRAME/PAGE translation logic
This is done by programming the stand alone flip-flops in the 74LS74 chip to set 1 after the system power on hardware
reset cycle.
U5B and U5C generates the write strobe for the registers.
U8,U9,U10 and U11 are the trick in the ROM mapper. They do translate the output of the mapper registers to actual memory
page in the ROM regarding the values in A14 and A15 (frame number in binary.)
74LS153 is a dual four-to-one addressable multiplexer with gate input. Eache chip can generate 2 multiplexed (translated)
address lines. You will notice that the mapper in the schematics does support 4096kb (32 megabits)
The usual size is 512kb (MA18). If you want to build one with 512kb just forget about U11 and use only the lower half of
U10.
The programming made by me in the Multiplexer inputs are:
Page 0: All multiplexers outputs 0.
Page 1: All multiplexers outputs the contents of the register FFFE (U6/U12A)
Page 2: All multiplexers outputs the contents of the register FFFE (U7/U12B)
Page 3: All multiplexers outputs 0 (But the address logic doesn't enables the ROM at this frame, does it ???) ;)
Personal notes:
On the frame 2 only version of this circuit I originally used the 74LS157 chip to do the translation. Since it was designed
only to support frame 2, it was cheaper to built that way.
This part of the circuit was the one took me more time to figure out, but man I only wasted two hours to ficure out which chips
I was going to use in the frame 2 only version of the mapper.
(If anyone has interest in that mapper, I can publish it's schematics too...)
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