Forums

is it safe to assume that when Cart_Enable, 'MC-F' and WR are asserted (active lows) that the paging registers have been accessed?

my logic is that 'MC-F' denotes an memory access to $C000 to $FFFF, of which RAM occupies $C000 to $DFFF and is mirrored
from $E000 to $FFFB, so the 8kB_RAM_CE is low and Cart_Enable is high for addresses $C000 to $FFFB, and the 8kB_RAM_CE
is high with Cart_Enable low for addresses $FFFC to $FFFF.

can i get a confirmation/correction on this.

Quote

> is it safe to assume that when Cart_Enable, 'MC-F' and WR are asserted (active lows) that the paging registers have been accessed?

> my logic is that 'MC-F' denotes an memory access to $C000 to $FFFF, of which RAM occupies $C000 to $DFFF and is mirrored
> from $E000 to $FFFB, so the 8kB_RAM_CE is low and Cart_Enable is high for addresses $C000 to $FFFB, and the 8kB_RAM_CE
> is high with Cart_Enable low for addresses $FFFC to $FFFF.

> can i get a confirmation/correction on this.

RAM is enabled for writes and reads to FFFC-FFFF, the value written will go to the bankswitch registers as well as RAM.

My Homepage

Quote

> RAM is enabled for writes and reads to FFFC-FFFF, the value written will go to the bankswitch registers as well as RAM.

is that so?
I hadn't figured that one out, believe it or not. I had figured the paging rom or external mapper had to answer the read request from the paging registers, which would have made the logic horrendously difficult to implement in hardware. Rather, for reads from $fffc-$ffff can be ignored by the mapper (and simple not send CE to the actual (ep)rom, so the mapper only needs to handle writes. That makes perfect sense.
I'm quite sure now that a 22v10-knockoff PLD could be programmed to work like at least a bank 2 only mapper, if only I knew of some affordable way of programming (in a hardware sense) a 22v10 PLD. (possibly even a 16r8?)

I'm not sure what is returned by a read to like, 0xFFFF, is the last written value had like bit 7 set (which is ignored by a masking when doing the mapping itself).

actually the logic is very simple. i've designed a full mapping system that supports mapping using pages 0, 1 and 2 with just 4 74 series logic chips

Quote

>
> > RAM is enabled for writes and reads to FFFC-FFFF, the value written will go to the bankswitch registers as well as RAM.

> is that so?
> I hadn't figured that one out, believe it or not. I had figured the paging rom or external mapper had to answer the read request from the paging registers, which would have made the logic horrendously difficult to implement in hardware. Rather, for reads from $fffc-$ffff can be ignored by the mapper (and simple not send CE to the actual (ep)rom, so the mapper only needs to handle writes. That makes perfect sense.
> I'm quite sure now that a 22v10-knockoff PLD could be programmed to work like at least a bank 2 only mapper, if only I knew of some affordable way of programming (in a hardware sense) a 22v10 PLD. (possibly even a 16r8?)

forgot to ask before, what is the exact behaviour of Cart_Enable? is it only asserted in the $0000 to $DFFF address range
or is it also asserted for $FFFC to $FFFF, because it's a bugger to test 16 address lines instead of just 2 (Cart_Enable and Mc-f)

> > is it safe to assume that when Cart_Enable, 'MC-F' and WR are asserted (active lows) that the paging registers have been accessed?

Quote

> > my logic is that 'MC-F' denotes an memory access to $C000 to $FFFF, of which RAM occupies $C000 to $DFFF and is mirrored
> > from $E000 to $FFFB, so the 8kB_RAM_CE is low and Cart_Enable is high for addresses $C000 to $FFFB, and the 8kB_RAM_CE
> > is high with Cart_Enable low for addresses $FFFC to $FFFF.

> > can i get a confirmation/correction on this.

> RAM is enabled for writes and reads to FFFC-FFFF, the value written will go to the bankswitch registers as well as RAM.

Author	Message
asynchronous Joined: 14 Aug 2000 Posts: 742 Location: Adelaide, Australia	detecting page register accesses in hardware Posted: Tue Aug 22, 2000 4:13 am
	is it safe to assume that when Cart_Enable, 'MC-F' and WR are asserted (active lows) that the paging registers have been accessed? my logic is that 'MC-F' denotes an memory access to $C000 to $FFFF, of which RAM occupies $C000 to $DFFF and is mirrored from $E000 to $FFFB, so the 8kB_RAM_CE is low and Cart_Enable is high for addresses $C000 to $FFFB, and the 8kB_RAM_CE is high with Cart_Enable low for addresses $FFFC to $FFFF. can i get a confirmation/correction on this.

Charles MacDonald Joined: 28 Sep 1999 Posts: 1197	Posted: Tue Aug 22, 2000 5:30 pm
Charles MacDonald Joined: 28 Sep 1999 Posts: 1197	Quote > is it safe to assume that when Cart_Enable, 'MC-F' and WR are asserted (active lows) that the paging registers have been accessed? > my logic is that 'MC-F' denotes an memory access to $C000 to $FFFF, of which RAM occupies $C000 to $DFFF and is mirrored > from $E000 to $FFFB, so the 8kB_RAM_CE is low and Cart_Enable is high for addresses $C000 to $FFFB, and the 8kB_RAM_CE > is high with Cart_Enable low for addresses $FFFC to $FFFF. > can i get a confirmation/correction on this. RAM is enabled for writes and reads to FFFC-FFFF, the value written will go to the bankswitch registers as well as RAM. My Homepage

Heliophobe Site Admin Joined: 25 Oct 1999 Posts: 2029 Location: Monterey, California	Does it really? Posted: Tue Aug 22, 2000 5:56 pm
	Quote > RAM is enabled for writes and reads to FFFC-FFFF, the value written will go to the bankswitch registers as well as RAM. is that so? I hadn't figured that one out, believe it or not. I had figured the paging rom or external mapper had to answer the read request from the paging registers, which would have made the logic horrendously difficult to implement in hardware. Rather, for reads from $fffc-$ffff can be ignored by the mapper (and simple not send CE to the actual (ep)rom, so the mapper only needs to handle writes. That makes perfect sense. I'm quite sure now that a 22v10-knockoff PLD could be programmed to work like at least a bank 2 only mapper, if only I knew of some affordable way of programming (in a hardware sense) a 22v10 PLD. (possibly even a 16r8?)

Zoop Joined: 24 Jun 1999 Posts: 1732 Location: Paris, France	Re: Does it really? Posted: Tue Aug 22, 2000 8:26 pm
	I'm not sure what is returned by a read to like, 0xFFFF, is the last written value had like bit 7 set (which is ignored by a masking when doing the mapping itself).

asynchronous Joined: 14 Aug 2000 Posts: 742 Location: Adelaide, Australia	page mapping hardware Posted: Thu Aug 24, 2000 2:18 am
	actually the logic is very simple. i've designed a full mapping system that supports mapping using pages 0, 1 and 2 with just 4 74 series logic chips Quote > > > RAM is enabled for writes and reads to FFFC-FFFF, the value written will go to the bankswitch registers as well as RAM. > is that so? > I hadn't figured that one out, believe it or not. I had figured the paging rom or external mapper had to answer the read request from the paging registers, which would have made the logic horrendously difficult to implement in hardware. Rather, for reads from $fffc-$ffff can be ignored by the mapper (and simple not send CE to the actual (ep)rom, so the mapper only needs to handle writes. That makes perfect sense. > I'm quite sure now that a 22v10-knockoff PLD could be programmed to work like at least a bank 2 only mapper, if only I knew of some affordable way of programming (in a hardware sense) a 22v10 PLD. (possibly even a 16r8?)

asynchronous Joined: 14 Aug 2000 Posts: 742 Location: Adelaide, Australia	Cart_Enable Posted: Thu Aug 24, 2000 2:32 am
	forgot to ask before, what is the exact behaviour of Cart_Enable? is it only asserted in the $0000 to $DFFF address range or is it also asserted for $FFFC to $FFFF, because it's a bugger to test 16 address lines instead of just 2 (Cart_Enable and Mc-f) > > is it safe to assume that when Cart_Enable, 'MC-F' and WR are asserted (active lows) that the paging registers have been accessed? Quote > > my logic is that 'MC-F' denotes an memory access to $C000 to $FFFF, of which RAM occupies $C000 to $DFFF and is mirrored > > from $E000 to $FFFB, so the 8kB_RAM_CE is low and Cart_Enable is high for addresses $C000 to $FFFB, and the 8kB_RAM_CE > > is high with Cart_Enable low for addresses $FFFC to $FFFF. > > can i get a confirmation/correction on this. > RAM is enabled for writes and reads to FFFC-FFFF, the value written will go to the bankswitch registers as well as RAM.

Forums

View topic - detecting page register accesses in hardware