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What does RISC stand for?

Chris :o)

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> What does RISC stand for?

Reduced Instruction Set C??
Basically means the CPU has few instructions each executing in a cycle. I guess someone on the forum should be able to tell you more about it, thought.

Quote

> What does RISC stand for?

> Chris :o)

Quote

> What does RISC stand for?

As unfnknblvbl (who I'm sure we'll all miss, Good luck!) stated, RISC stands for Reduced Instruction Set Computer. This is in contrast to CISC (Complex Instruction Set Computer). RISC and CISC are two different philosophies about how (micro) processors should be designed.

In the past, most software development was done in assembly language. CISC machines provide a tremendous variety of instructions and many special-purpose instructions to aid the assembly language programmer. Additionally, memory was scarce, so CISC architectures typically have instructions of varying sizes to squeeze as much space as possible out of the limited available memory. There are two disadvantages to CISC architectures. The first is that these architectures are not "orthogonal", there are many special-purpose instructions and many instructions that can only use certain registers, making it difficult for compilers (which are used more today) to generate efficient code. The other disadvantage is that significant decode logic is necessary to decode the variety of instructions available and to decode all the special cases. The amount of decode logic can hurt the performance of CISC machines. The Z80 and x86 are two examples of CISC processors.

Today, most software development is done in high-level languages, compilers generate the actual machine code. Also, memory is more plentiful, so many designs have migrated to a RISC approach. RISC designs are "orthogonal": there are very few special cases, and nearly any register can be used by any instruction. RISC designs typically employ a LOAD/STORE approach, meaning that only the LOAD and STORE instructions address memory, all other instructions must use data in registers (contrast this to the Z80 instruction set). A LOAD/STORE approach is much easier for compilers to deal with. Add to this the fact that any register can be used with any instruction, and it's clear why compilers can (more easily) generate efficient code for RISC machines. The "reduced" part implies that RISC machines have fewer instructions, thus less decode logic is necessary, allowing for a more streamlined (and consequently faster) design. However, to simplify the decode, most instructions are fixed-width (4 bytes) which may be wasteful for some instructions. Couple this with the fact that it takes more instructions to perform the same task as a single CISC instruction, and you'll see that RISC program requires more memory than a comparable CISC program. The R3000 (PlayStation) and I believe Power PC are examples of RISC processors.

Understand one thing though, in contrast to what many people would have you believe there is nothing inherently better about one approach or the other. They are simply two different design styles used to meet different needs. It just turns out that RISC is more appropriate in today's computing environment. This does not mean that RISC will always be better. There are many current CISC processors that can out-perform their RISC counterparts.

Hope this helps.

Eric Quinn

Quote

> Today, most software development is done in high-level languages, compilers generate the actual machine code. Also, memory is more plentiful, so many designs have migrated to a RISC approach. RISC designs are "orthogonal": there are very few special cases, and nearly any register can be used by any instruction. RISC designs typically employ a LOAD/STORE approach, meaning that only the LOAD and STORE instructions address memory, all other instructions must use data in registers (contrast this to the Z80 instruction set). A LOAD/STORE approach is much easier for compilers to deal with. Add to this the fact that any register can be used with any instruction, and it's clear why compilers can (more easily) generate efficient code for RISC machines. The "reduced" part implies that RISC machines have fewer instructions, thus less decode logic is necessary, allowing for a more streamlined (and consequently faster) design. However, to simplify the decode, most instructions are fixed-width (4 bytes) which may be wasteful for some instructions. Couple this with the fact that it takes more instructions to perform the same task as a single CISC instruction, and you'll see that RISC program requires more memory than a comparable CISC program. The R3000 (PlayStation) and I believe Power PC are examples of RISC processors.

Yep, the PowerPC series are RISC chips.
Another feature of RISC chips is that they tend to delegate specialized tasks to specialized coprocessors (which may be on the same chips as the CPU itself), such as the Altivec extensions of the G4, or the Geometric Transform Engine (er, something like that) of the Playstation.
Other RISC chips in common use are the MIPS series from SGI (the R3000A and R4000-whatever in the N64), the SH series from Hitachi (SH-2 in the Saturn, SH-4 in the Dreamcast). And a new one you may be hearing about more, the Transmeta 'Crusoe'. The PIC series of microcontrollers is also considered a RISC chip, as it has a small but flexible set of opcodes that are generally symmetrical, that is, you can usually specify any registers for operands. Generally.
Another advantage of RISC chips is the simplified design generally means less power consumption (other factors affect this) which make them very useful for portable systems, such as WinCE devices, palm pilots, and many others.

A feature common to RISC chips is that they don't use status flags the way CISC chips do. Generally, they either have no status flags whatsoever, or just a few very special ones that aren't used in the general instruction set. Carry, Zero, Negative, etc. flags no longer have to be set and tested for each instruction, which makes them easier to emulate, even with dynamic recompiling cores.

Author	Message
Consolemu Guest	Quick Question Posted: Tue May 23, 2000 5:22 am
Consolemu Guest	What does RISC stand for? Chris :o)

Zoop Joined: 24 Jun 1999 Posts: 1732 Location: Paris, France	Posted: Tue May 23, 2000 9:12 am
	Quote > What does RISC stand for? Reduced Instruction Set C?? Basically means the CPU has few instructions each executing in a cycle. I guess someone on the forum should be able to tell you more about it, thought.

unfnknblvbl Joined: 12 Jul 1999 Posts: 891	Reduced Instruction Set Computer nt Posted: Tue May 23, 2000 2:46 pm
unfnknblvbl Joined: 12 Jul 1999 Posts: 891	Quote > What does RISC stand for? > Chris :o)

Eric R. Quinn Joined: 18 Sep 1999 Posts: 498 Location: Portland, Oregon USA	Re: Quick Question, Long Answer Posted: Tue May 23, 2000 4:28 pm
	Quote > What does RISC stand for? As unfnknblvbl (who I'm sure we'll all miss, Good luck!) stated, RISC stands for Reduced Instruction Set Computer. This is in contrast to CISC (Complex Instruction Set Computer). RISC and CISC are two different philosophies about how (micro) processors should be designed. In the past, most software development was done in assembly language. CISC machines provide a tremendous variety of instructions and many special-purpose instructions to aid the assembly language programmer. Additionally, memory was scarce, so CISC architectures typically have instructions of varying sizes to squeeze as much space as possible out of the limited available memory. There are two disadvantages to CISC architectures. The first is that these architectures are not "orthogonal", there are many special-purpose instructions and many instructions that can only use certain registers, making it difficult for compilers (which are used more today) to generate efficient code. The other disadvantage is that significant decode logic is necessary to decode the variety of instructions available and to decode all the special cases. The amount of decode logic can hurt the performance of CISC machines. The Z80 and x86 are two examples of CISC processors. Today, most software development is done in high-level languages, compilers generate the actual machine code. Also, memory is more plentiful, so many designs have migrated to a RISC approach. RISC designs are "orthogonal": there are very few special cases, and nearly any register can be used by any instruction. RISC designs typically employ a LOAD/STORE approach, meaning that only the LOAD and STORE instructions address memory, all other instructions must use data in registers (contrast this to the Z80 instruction set). A LOAD/STORE approach is much easier for compilers to deal with. Add to this the fact that any register can be used with any instruction, and it's clear why compilers can (more easily) generate efficient code for RISC machines. The "reduced" part implies that RISC machines have fewer instructions, thus less decode logic is necessary, allowing for a more streamlined (and consequently faster) design. However, to simplify the decode, most instructions are fixed-width (4 bytes) which may be wasteful for some instructions. Couple this with the fact that it takes more instructions to perform the same task as a single CISC instruction, and you'll see that RISC program requires more memory than a comparable CISC program. The R3000 (PlayStation) and I believe Power PC are examples of RISC processors. Understand one thing though, in contrast to what many people would have you believe there is nothing inherently better about one approach or the other. They are simply two different design styles used to meet different needs. It just turns out that RISC is more appropriate in today's computing environment. This does not mean that RISC will always be better. There are many current CISC processors that can out-perform their RISC counterparts. Hope this helps. Eric Quinn

Heliophobe Site Admin Joined: 25 Oct 1999 Posts: 2029 Location: Monterey, California	Re: Quick Question, Long Answer Posted: Tue May 23, 2000 4:48 pm
	Quote > Today, most software development is done in high-level languages, compilers generate the actual machine code. Also, memory is more plentiful, so many designs have migrated to a RISC approach. RISC designs are "orthogonal": there are very few special cases, and nearly any register can be used by any instruction. RISC designs typically employ a LOAD/STORE approach, meaning that only the LOAD and STORE instructions address memory, all other instructions must use data in registers (contrast this to the Z80 instruction set). A LOAD/STORE approach is much easier for compilers to deal with. Add to this the fact that any register can be used with any instruction, and it's clear why compilers can (more easily) generate efficient code for RISC machines. The "reduced" part implies that RISC machines have fewer instructions, thus less decode logic is necessary, allowing for a more streamlined (and consequently faster) design. However, to simplify the decode, most instructions are fixed-width (4 bytes) which may be wasteful for some instructions. Couple this with the fact that it takes more instructions to perform the same task as a single CISC instruction, and you'll see that RISC program requires more memory than a comparable CISC program. The R3000 (PlayStation) and I believe Power PC are examples of RISC processors. Yep, the PowerPC series are RISC chips. Another feature of RISC chips is that they tend to delegate specialized tasks to specialized coprocessors (which may be on the same chips as the CPU itself), such as the Altivec extensions of the G4, or the Geometric Transform Engine (er, something like that) of the Playstation. Other RISC chips in common use are the MIPS series from SGI (the R3000A and R4000-whatever in the N64), the SH series from Hitachi (SH-2 in the Saturn, SH-4 in the Dreamcast). And a new one you may be hearing about more, the Transmeta 'Crusoe'. The PIC series of microcontrollers is also considered a RISC chip, as it has a small but flexible set of opcodes that are generally symmetrical, that is, you can usually specify any registers for operands. Generally. Another advantage of RISC chips is the simplified design generally means less power consumption (other factors affect this) which make them very useful for portable systems, such as WinCE devices, palm pilots, and many others. A feature common to RISC chips is that they don't use status flags the way CISC chips do. Generally, they either have no status flags whatsoever, or just a few very special ones that aren't used in the general instruction set. Carry, Zero, Negative, etc. flags no longer have to be set and tested for each instruction, which makes them easier to emulate, even with dynamic recompiling cores.

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