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I've made a quick ROM that measures how slow a mapper is, in essence how many instructions it takes to switch banks. A correctly implemented mapper should obviously have a zero instruction delay but this program can help you measure how off-the-mark you still are.

It tests against the SLOT2 bank from the SLOT0 area. First column measures the BANK0->BANK2 switch and the second column measures the BANK2->BANK0 switch. Min/Max measure the minimum/maximum measured delay and Acc measures the accumulated delay over the 128 iterations of the test.

test-mapper-speed000.png (6.72 KB)

test-rom.7z (3.23 KB)

Like the abuse test, i test this on my custom mapper. Succesfull !

I have the nice "Congrat, you did it ;)" message, with all measured delay to 0x00.

Therefore, no one game larger than 32KB want launch. Can you confirm that games only use slot 2 ?

Maybe the checksum routine of BIOS use the other slot ? (i obtain the ugly "SOFTWARE ERROR" screen)

Thanks. (Again).

Games I tested successfuly on my custom, SLOT2-Only mapper so far have been "Sonic the hedgehog 2" and "Marble madness". I would suggest you use those to test your mapper.

Regarding the speed test, this is largely untested code so it could be passing when it should not. I should try it on my Slow PIC18-based mapper first. Just checked and it uses SLOT2 while ignoring any use of SLOT1. I know from experience on my own mapper that an improper implementation of SLOT1 can make the BIOS check fail, that is why I have it fixed to page 1 for now.

Hello,

I try "Sonic the hedgehog 2" and this didn't work. I didn't test "Marble madness" for now. Test soon.

When you say "I have it fixed to page 1 for now." you mean that slot 1 represent 0x4000 to 0x8000 of ROM (sorry Im lost, some people begin count page at 1 and other at 0) ? If yes, I'm in the same case.

Yes, it means that the SLOT1 address maps directly to the ROM address. If the Test passes but the game does not then I should be worried since that should not happen :P

I'm worried :P

I didn't understand why. Your abuse test on bank 2 and your speed test pass successfully. And 32K ROM work successfully, I can assume that slot 0 and slot 1 map correctly to ROM 0x0000-0x8000.

I can read back the entire 512K of "Sonic the hedgehog 2" of my SRAM using mapper protocol, assuming that the mapper and SRAM hold correctly the ROM.

The only reason I see for now is that my SMS have BIOS that check CheckSum by using slot 1 instead of slot 2. Its an US SMS 2 with AlexKidd.

I will test on my EU SMS 2 see if I obtain any difference.

Ok this is a digging message but
I have found my problem so better late than never. Late because life has forced me to pause my passion for some time. But I recently managed to work on it and:

My mapper is 3 state (the register part), and I used 10k pulldown resistor : The faling edge when accessing from bank to unmapped aera was on the limit of taking one CPU clock cycle. It was on the third bit of the mapper that the timing was too high, hence the bug on some software and not all.

Changing by 1k res was the solution, now the mapper work perfectly fine: Now I have a pretty falling edge.

Once I have a nice demo I'll create a thread, but here is my SMS dev board V0:

SMSShield5.jpg (405.6 KB)

Author	Message
NeonMan Joined: 24 Sep 2013 Posts: 141	Mapper test ROM (for mapper devs) Posted: Wed Nov 16, 2016 11:43 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	I've made a quick ROM that measures how slow a mapper is, in essence how many instructions it takes to switch banks. A correctly implemented mapper should obviously have a zero instruction delay but this program can help you measure how off-the-mark you still are. It tests against the SLOT2 bank from the SLOT0 area. First column measures the BANK0->BANK2 switch and the second column measures the BANK2->BANK0 switch. Min/Max measure the minimum/maximum measured delay and Acc measures the accumulated delay over the 128 iterations of the test. test-mapper-speed000.png (6.72 KB) test-rom.7z (3.23 KB)

leviatan Joined: 24 Oct 2016 Posts: 26	Posted: Thu Nov 17, 2016 7:21 pm
leviatan Joined: 24 Oct 2016 Posts: 26	Like the abuse test, i test this on my custom mapper. Succesfull ! I have the nice "Congrat, you did it ;)" message, with all measured delay to 0x00. Therefore, no one game larger than 32KB want launch. Can you confirm that games only use slot 2 ? Maybe the checksum routine of BIOS use the other slot ? (i obtain the ugly "SOFTWARE ERROR" screen) Thanks. (Again).

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Thu Nov 17, 2016 7:58 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	Games I tested successfuly on my custom, SLOT2-Only mapper so far have been "Sonic the hedgehog 2" and "Marble madness". I would suggest you use those to test your mapper. Regarding the speed test, this is largely untested code so it could be passing when it should not. I should try it on my Slow PIC18-based mapper first. Just checked and it uses SLOT2 while ignoring any use of SLOT1. I know from experience on my own mapper that an improper implementation of SLOT1 can make the BIOS check fail, that is why I have it fixed to page 1 for now.

leviatan Joined: 24 Oct 2016 Posts: 26	Posted: Fri Nov 18, 2016 8:39 am
leviatan Joined: 24 Oct 2016 Posts: 26	Hello, I try "Sonic the hedgehog 2" and this didn't work. I didn't test "Marble madness" for now. Test soon. When you say "I have it fixed to page 1 for now." you mean that slot 1 represent 0x4000 to 0x8000 of ROM (sorry Im lost, some people begin count page at 1 and other at 0) ? If yes, I'm in the same case.

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Fri Nov 18, 2016 9:40 am
NeonMan Joined: 24 Sep 2013 Posts: 141	Yes, it means that the SLOT1 address maps directly to the ROM address. If the Test passes but the game does not then I should be worried since that should not happen :P

leviatan Joined: 24 Oct 2016 Posts: 26	Posted: Fri Nov 18, 2016 10:55 am
leviatan Joined: 24 Oct 2016 Posts: 26	I'm worried :P I didn't understand why. Your abuse test on bank 2 and your speed test pass successfully. And 32K ROM work successfully, I can assume that slot 0 and slot 1 map correctly to ROM 0x0000-0x8000. I can read back the entire 512K of "Sonic the hedgehog 2" of my SRAM using mapper protocol, assuming that the mapper and SRAM hold correctly the ROM. The only reason I see for now is that my SMS have BIOS that check CheckSum by using slot 1 instead of slot 2. Its an US SMS 2 with AlexKidd. I will test on my EU SMS 2 see if I obtain any difference.

leviatan Joined: 24 Oct 2016 Posts: 26	Posted: Thu Jan 11, 2024 10:52 am
leviatan Joined: 24 Oct 2016 Posts: 26	Ok this is a digging message but I have found my problem so better late than never. Late because life has forced me to pause my passion for some time. But I recently managed to work on it and: My mapper is 3 state (the register part), and I used 10k pulldown resistor : The faling edge when accessing from bank to unmapped aera was on the limit of taking one CPU clock cycle. It was on the third bit of the mapper that the timing was too high, hence the bug on some software and not all. Changing by 1k res was the solution, now the mapper work perfectly fine: Now I have a pretty falling edge. Once I have a nice demo I'll create a thread, but here is my SMS dev board V0: SMSShield5.jpg (405.6 KB)

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