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Hello,

I read in the technical doc that VRAM reading is buffered.
But what about RAM writing during the display ? It is highly probable that VRAM also needs to be accessed to print pixels.

The pixel clock seems to be half of the VDP clock. Is there a cycle "dedicated" for VRAM updating (if needed...) and the other for the display ?

Thanks !

Yes, there’s a free “slot” for CPU VRAM access every so often during active display - I think every 32 pixels or so, but the details are complicated.

I'd say probably once every 38 pixels, as if you write to VRAM every 25 CPU cycles you can corrupt VRAM, if you write every 26 CPU cycles you won't.

but it's likely more complicated than that. You probably can write slightly faster during h_blank, but I'm just supposing that.

or it could be the other way around

Author	Message
cgyed.cgyed Joined: 10 Feb 2020 Posts: 6	VRAM writing during display Posted: Mon Feb 10, 2020 2:51 pm
cgyed.cgyed Joined: 10 Feb 2020 Posts: 6	Hello, I read in the technical doc that VRAM reading is buffered. But what about RAM writing during the display ? It is highly probable that VRAM also needs to be accessed to print pixels. The pixel clock seems to be half of the VDP clock. Is there a cycle "dedicated" for VRAM updating (if needed...) and the other for the display ? Thanks !

Maxim Site Admin Joined: 19 Oct 1999 Posts: 14734 Location: London	Posted: Mon Feb 10, 2020 5:19 pm
	Yes, there’s a free “slot” for CPU VRAM access every so often during active display - I think every 32 pixels or so, but the details are complicated.

sverx Joined: 05 Sep 2013 Posts: 3823 Location: Stockholm, Sweden	Posted: Mon Feb 10, 2020 6:25 pm
	I'd say probably once every 38 pixels, as if you write to VRAM every 25 CPU cycles you can corrupt VRAM, if you write every 26 CPU cycles you won't. but it's likely more complicated than that. You probably can write slightly faster during h_blank, but I'm just supposing that. or it could be the other way around

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