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Behaviour of #CE signal.
Posted: Mon Sep 22, 2014 10:40 am
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I can't find on the documentation if the cartridge #CE signal goes active once the cartridge slot is selected or if it goes active on every read/write cycle.
If #CE goes active on every read/write cycle I'd like to know if it goes active after or before the corresponding #WR/#RD signal. I don't have access to a fast enough logic analyzer (yet) but I'd like to document all this stuff eventually. |
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Posted: Mon Sep 22, 2014 1:53 pm |
CE is generated from MREQ and the enable bit (s) in the I/O chip. So it is active any time MREQ is asserted, regardless of WR, RD, or other signals. I checked with a logic analyzer.
A lot of my notes about these hardware topics are buried in the SMS Power forums, maybe I should compile them together. There's times when I've forgotten something just to find I had posted about it years ago. :) |
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Posted: Mon Sep 22, 2014 2:01 pm |
Thanks!
Timing info and diagrams are very useful, a compilation of those would be great. |
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Posted: Mon Sep 22, 2014 4:07 pm |
For Z80 related timing you can get a lot of info from the Mostek Z80 datasheet. I host it on my website:
http://www.db-elec.com/home/technical-info/sms/datasheets |
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Posted: Tue Jul 09, 2019 9:17 am |
is CE active even when accessing the system's RAM, i.e., is it independent from the address? | |
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Behaviour of #CE signal.
Posted: Wed Jul 10, 2019 3:27 am
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Yes, it is totally independent of address and follows /MREQ for the entire address range, including the part where the SYS RAM is mapped. | |
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Posted: Thu Jul 18, 2019 7:27 am |
Sorry for the delay in the reply, thank you! | |