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VRAM access speed during display period
Posted: Mon Mar 17, 2003 11:11 am Last edited by Maxim on Fri Oct 21, 2011 9:58 am; edited 1 time in total
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I was inspired by ZexAll to create a self-modifying demo to test how much delay is needed beteeen VRAM writes during the active display period to avoid corruption. My code basically boils down to this:
--:ld a,(ix+0)
ld b,(ix+1)
out (c),a ; fast writing
DelayCode:.dsb DelaySize 0
out (c),b
and I patch the 3 bytes at DelayCode with the following:
.section "Delay codes" free
; Delay codes for separating VRAM writes
; MUST NOT modify bc, ix, hl
; Reference:
; opcode size cycles
; nop 1 4
; ld a,(hl) 1 7
; ld a,i 2 9
; add a,nn 2 7
; inc iy 2 10
DelayCodes:
nop ; 12 cycles
nop ; (1,4 + 1,4 + 1,4 = 3,12)
nop
ld a,i ; 13 cycles
nop ; (2,9 + 1,4 = 3,13)
ld a,(hl) ; 14 cycles
add a,0 ; (1,7 + 2,7 = 3,14)
add a,(hl) ; 15 cycles
nop ; (1,7 + 1,4 + 1,4 = 3,15)
nop
ld a,(hl) ; 16 cycles
ld a,i ; (1,7 + 2,9 = 3,16)
inc iy ; 17 cycles
ld a,(hl) ; (2,10 + 1,7 = 3,17)
add a,(hl) ; 18 cycles
add a,(hl) ; (1,7 + 1,7 + 1,4 = 3,18)
nop
.ends
I relied on the official Z80 documentation to find suitable opcodes and for their timings, so any errors there will have followed through. Anyway, I ran it on my SMS2 and got the following result:
Corruption occurs at the 12 and 13 cycle intervals, but not at 14 and above. Therefore, including the out (c),r instruction's length which is given as 12 cycles, the minimum delay between writes is 26 cycles. So:
Official Mark III docs: Wait 16 during VBlank, 29 during display
Official GG docs: No wait needed during VBlank, 28 during display
My test: No wait needed during VBlank, 26 during display
Anyway, I think it's worth testing on different VDP revisions. Anyone who can do so, please email me for a binary.
[Edit: the binary and source is most likely lost now.]
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