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View topic - SC-3000 MITEC-2 reverse engineered

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  • Joined: 14 Nov 2022
  • Posts: 14
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SC-3000 MITEC-2 reverse engineered
Post Posted: Fri Dec 02, 2022 8:53 am
Hey all!

Just announcing that I have completed reverse engineering and recreation of the custom gate array IC inside the SC-3000, the MITEC-2

You can find the Verilog source, along with a Kicad project for simple PCB design, at https://github.com/silvervest/mitec2

I tried to make the Verilog fairly self-documenting, but I've included my research done and the equations derived in relatively plain english below.
I've also put together a YT video detailing the repair of the system that led me down the path to where we are today, which shows a working board as well


Many thanks go to the folks that helped me out in the other thread where we figured out the RAS/CAS logic and cleaned up a lot.
https://www.smspower.org/forums/19266-MITECReverseEngineerLogic

Let me know if you have any comments or feedback! Always happy to discuss :)

Input Pins
==========
/NMIN    - "Reset" key, held high via 4.7k to R1
/RD, /WR - Read/write direction from Z80
/MREQ    - Memory request
/IORQ    - I/O request
/RFSH    - CPU memory refresh
A6       - Used as /CS for VDP
A7       - Used as /CS for CE89
A14      - Used for multiplexing external DRAM
A15      - Used as /CS for RAM/ROM

Output Pins
===========
/NMI         - CPU interrupt
/MEMR, /MEMW - Onboard SRAM read/write
/IOR, /IOW   - PPI (8255) read/write
/CSR, /CSW   - VDP (TMS9918/TMS9929) read/write
/CE89        - PSG (SN76489) chip enable
/CSSRAM      - Onboard SRAM chip enable
/CEROM2      - Cart ROM chip enable
/CAS1, /CAS2 - External DRAM column strobe, multiplexed
/RAS1, /RAS2 - External DRAM row strobe, multiplexed
/MUX         - External DRAM multiplexer
RAMA7        - Replaces regular A7 in external DRAM

Detailed Output Pin Definitions and Equations
=============================================
/NMI
Inputs used: /NMIN
    This is used to interrupt the CPU's /NMI, and signal things like resetting programs or pausing games.
    It is activated by pressing the RESET key on the keyboard, which pulls the /NMIN pin LOW.
    This input is then debounced inside the MITEC-2 and output here

/MEMR, /MEMW
Inputs used: /MREQ, /RD, /WR
    These pins are used to toggle /OE and /WE on IC3, the onboard SRAM, to remember things.
    When /MREQ is brought LOW, along with one of /RD or /WR, the respective /MEMR or /MEMW pins are brought LOW, signalling the SRAM to read or write.
    /CS on the SRAM is handled elsewhere by the /CSSRAM pin (detailed later)

/IOR, /IOW
Inputs used: /MREQ, /IORQ, /RD, /WR, A6, A7
    These pins are used to toggle /RD and /WR on IC5, the PPI, for general input/output things.
    When /IORQ is brought LOW, along with one of /RD or /WR, the respective /IOR or /IOW pins are brought LOW, signalling the PPI to read or write.
    MREQ A6 and A7 must all stay HIGH to not overlap other enable pins

/CSR, /CSW
Inputs used: /MREQ, RFSH, /RD, /WR, A6, A7
    These pins are used to toggle /CSR and /CSW on IC9, the VDP, to draw pretty things.
    When A6 is brought LOW and RFSH brought HIGH, along with one of /RD or /WR, the respective /CSR or /CSW pins are brought LOW, signalling the VDP to read or write.
    MREQ and A7 must stay HIGH to not overlap other enable pins.
    RFSH seems random in this equation, but was found via logic analysis and deemed necessary through testing.

/CE89
Inputs used: /MREQ, /IORQ, /RD, /WR, A6, A7
    This pin is used to toggle /CE on IC4, the PSG, to make beeps and boops.
    When A7, /WR and /IORQ are brought LOW, /CE89 will be pulled LOW, signalling the PSG to enable.
    MREQ and A6 must stay HIGH to not overlap other enable pins.
    When the PSG begins outputting audio, it pulls it's READY (CPU /WAIT) pin LOW pausing CPU cycles until it has completed, at which point READY (CPU /WAIT) is brought HIGH and cycles continue. This is unrelated to the MITEC, but still interesting!

/CSSRAM
Inputs used: /MREQ, A15
    This pin is used to toggle /CS on IC3, the onboard SRAM, to remember things.
    When MREQ is brought LOW and A15 is held HIGH, /CSSRAM is pulled LOW, signalling the SRAM to enable.
    This appears to be identical to /CEROM2, which doesn't make sense, but it works in practice.

/CEROM2
Inputs used: /MREQ, A15
    This pin is used to toggle /CS on external cart ROMs.
    When MREQ is brought LOW and A15 is held HIGH, /CEROM2 is pulled LOW, signalling the SRAM to enable.
    This appears to be identical to /CSSRAM, which doesn't make sense, but it works in practice.

/RAS1, /RAS2, /CAS1, /CAS2, /MUX
Inputs used: /MREQ, /RD, /WR, RFSH, A14, A15
    This combination of pins is used to control exterrnal DRAM on cartridges that provide it (such as BASIC carts)
    When /MREQ is pulled low, and either RFSH is pulled LOW, or A15 is pulled HIGH and either /RD or /WR are pulled LOW, /RAS1/2 will be pulled LOW. 1 or 2 is determined by A15, where /RAS1 is used when A14 is LOW and /RAS2 when A14 is HIGH.
    Shortly after /RAS is pulled LOW, RFSH will be pulled HIGH and either /RD or /WR along with /MREQ will be pulled low, at which point /MUX will be pulled LOW.
    Shortly after /MUX is LOW, the matching /CAS1/2 will be pulled LOW.
    A14 along with the 1/2 combinations on RAS/CAS pins, are used to control up to 2 banks of DRAM.
    The timing of these outputs is detailed on pages 11-12 of service manual.

RAMA7
Inputs used: /RFSH, A7
    The main CPU A7 pin is combined with RFSH for use when accessing external cart DRAM. The purpose is unknown.
    When A7 and RFSH are HIGH, RAMA7 is pulled HIGH.
    In the BASIC IIIB cartidge, RAMA7 is pulled LOW when /MUX is HIGH.
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  • Joined: 25 Feb 2013
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Post Posted: Fri Dec 02, 2022 2:31 pm
Gorgeous work!Did you try if a software which invokes halt is woken up by a debounced nmi?
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  • Joined: 05 Jun 2010
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Post Posted: Sat Dec 03, 2022 1:28 am
Very nice work!
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  • Joined: 14 Nov 2022
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Post Posted: Sat Dec 03, 2022 5:28 am
Thanks!

kamillebidan wrote
Gorgeous work!Did you try if a software which invokes halt is woken up by a debounced nmi?

Not sure that specifically, but the debounced NMI is definitely picked up and resets BASIC and pauses certain game carts.
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  • Joined: 10 Dec 2009
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Post Posted: Sun Dec 04, 2022 1:14 pm
Nice work mate!
.
As far as I know Zippy Race game put the NMI handling to the limit. You can try it out to be sure everything is ok.

S.


silvervest wrote
Thanks!

kamillebidan wrote
Gorgeous work!Did you try if a software which invokes halt is woken up by a debounced nmi?

Not sure that specifically, but the debounced NMI is definitely picked up and resets BASIC and pauses certain game carts.
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