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- Joined: 25 Feb 2013
- Posts: 384
- Location: Osaka
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SF-7000 mirrors
Posted: Wed Nov 17, 2021 10:57 am
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The manual reports the standard IO ports for the SF-7000.
However, it makes sense to assume that the address decoding logic is reduced to the minimum possible.
MAME has no mirrors. See the output of this simple program. I would however assume that in the actual hardware there are mirrors, as shown in the "mirrored.png" picture. Does anyone have a real SF-7000 to test?
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- Joined: 10 Dec 2009
- Posts: 115
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It's mirrored.
Posted: Wed Nov 17, 2021 12:21 pm
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kamillebidan wrote The manual reports the standard IO ports for the SF-7000.
However, it makes sense to assume that the address decoding logic is reduced to the minimum possible.
MAME has no mirrors. See the output of this simple program. I would however assume that in the actual hardware there are mirrors, as shown in the "mirrored.png" picture. Does anyone have a real SF-7000 to test?
It's mirrored but software doesn't use any other ports except E0-E9. Your test could output strange results because not every port in that range is an input port.
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- Joined: 25 Feb 2013
- Posts: 384
- Location: Osaka
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Posted: Wed Nov 17, 2021 3:03 pm
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Is this table derived from the real hardware or just on speculation as I did above?
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- Joined: 10 Dec 2009
- Posts: 115
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Posted: Sat Nov 20, 2021 1:52 pm
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kamillebidan wrote Is this table derived from the real hardware or just on speculation as I did above?
Chip selection of SF-7000 is done using one side of a 74LS139. Only A4-A2 address pins are used. Picture from real hardware.
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- Site Admin
- Joined: 19 Oct 1999
- Posts: 14745
- Location: London
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Posted: Sat Nov 20, 2021 2:35 pm
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Ah, so there’s effectively three inconsistent chip selection mechanisms tied to those bits and it requires some care from the software to set the irrelevant bits consistently. However, as is often the case with emulation, implementing the appropriate logic is as simple as bit masks and sometimes combining values as they collide on the bus.
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- Joined: 10 Dec 2009
- Posts: 115
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Posted: Sat Nov 20, 2021 3:20 pm
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Maxim wrote Ah, so there’s effectively three inconsistent chip selection mechanisms tied to those bits and it requires some care from the software to set the irrelevant bits consistently. However, as is often the case with emulation, implementing the appropriate logic is as simple as bit masks and sometimes combining values as they collide on the bus.
Exactly. Consistency is done in software ensuring A7-A5 address bits to 1.
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- Joined: 25 Feb 2013
- Posts: 384
- Location: Osaka
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Posted: Mon Nov 22, 2021 3:04 pm
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siriokds wrote kamillebidan wrote Is this table derived from the real hardware or just on speculation as I did above?
Chip selection of SF-7000 is done using one side of a 74LS139. Only A4-A2 address pins are used. Picture from real hardware.
Did you get an SF-7000? Congratulations!
Or is it just the publicly available picture? From seeing the 74LS139 that was my supposition as well (hence the first screenshot) but, as you may have seen, most of the connections of those gates go under the ICs and the traces cannot be traced just from the publicly available pics.
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