|
ForumsSega Master System / Mark III / Game GearSG-1000 / SC-3000 / SF-7000 / OMV |
Home - Forums - Games - Scans - Maps - Cheats - Credits Music - Videos - Development - Hacks - Translations - Homebrew |
Author | Message |
---|---|
|
Timing of VRAM access "slots" during active/passive display
Posted: Tue Sep 29, 2020 5:01 pm
|
We were discussing https://www.smspower.org/forums/14599-HowManyBytesCanIWriteToVRAMPerFrame in the chat and having some confusion. It seems like the VDP is able to service VRAM accesses at variable rates during different parts of the display because it needs some of that access for itself. There’s a disparity between the pixel output rate (342 per line including horizontal blanking/borders) and CPU clock rate (228 cycles per line), which adds confusion.
I guess the idea is that there is a VRAM “access slot” every 4 pixels at all times; during the “passive” display time these are all available for the CPU but as that’s every 2.62 CPU cycles we cannot take advantage of it. During the rendered part of the display there are apparently “free slots” every 32 pixels (21.33 CPU cycles) but during the other parts there are fewer/none; this manages to add to 10 slots per line but where are they? Are there 9 aligned exactly to the 256 rendered pixels, plus one in the “hblank”, or are there 8 + 2? Either way, they are not uniformly spaced - and how does this then map to the 26 CPU cycles we use to space writes (39 pixels)? Does this 26 cycles spacing just manage to cover the worst-case “slot” spacing, at the cost of not actually managing to hit all 10 slots per line? Could you go faster if you synchronised to the horizontal interrupt? I guess this is a lot of questions. More simply, where do the “free slots” fit timing-wise with the VDP line timing? |
|
|
Posted: Wed Sep 30, 2020 2:42 am |
For what it's worth, the Mega Drive scene has looked into Mode 4 access timings behavior on the Mega Drive VDP pretty thoroughly.
Tiido also seems to confirm the behavior is the same on a Master System, at least with the VDP his SMSII had. (I actually need to thank a friend for finding this information, I'm just linking what they found.) |
|
|
Posted: Wed Sep 30, 2020 7:30 am |
Quoting for posterity:
If I understand correctly then that gives 11 “external slots” per line, but as many are grouped, they are hard to use from the Z80, but may be theoretically useable in a “bus mastering” scenario. |
|
|
Posted: Wed Sep 30, 2020 9:29 am |
I think it's saying that we have 11 "External Slot" per line plus the 8 that are into the Background Render Block, one each.
The question remain - is during vblank doing more than simply "External Slot"s? edit: also, I suspect those two "HSYNC..." lines are just annotations, so not using a real slot, as the sum would be 346 'operations' instead of 342. edit2: also, these lines confirm that the VDP is indeed accessing VRAM with 16-bits reads (and also explains why SAT is organized the way we know):
|
|