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Edit: Design finished, built and tested. Get the board design and firmware here

Two years ago I made a SEGA card clone with a mapper clone made out of discrete components, the bad part is that I made it with a not-really-legally-licensed and proprietary CAD solution (Proteus) and would put in trouble other people if I released it as is, so this time I'm fixing some issues it had, moving the mapper connector to a single 40pin header as to allow development of Hardware, and using KiCAD instead of any proprietary solution.

I would like some feedback on this part of the circuit, which should work as a plain 32K cartridge, especially the ROM #CE line, which I'm not really sure if that's the correct way to use it, even though "it works" on the current revision of the board, and the chosen board dimensions, which are slightly smaller (a few dozen Thou narrower) since current board revision "scratches" the SMS port sides, board thickness increased from 1.6mm (which barely works) to 2mm (closer to real card thickness)

The mapper will attach to the pin header, and will be released in a similar fashion later on this same thread. Separating it makes the boards cheaper to manufacture and allows the card port to be used as a general purpose peripheral port.

Note that, with no mapper attached, you can put 5 jumpers between pins 32 to 40 and 31 to 39 to set ROM upper address to Zero and ROM A14 to Z80 A14, giving 32K of address space.

Attached to this message are design files and PDF prints of them. Feedback welcome! :)

sega_flash_card_v2.zip (170.94 KB)

Mapper module ready for use. No more need for "Donnor Cartridges" or FPGAs. At least for SLOT1/2 games. Also, while intended to be used with the SEGA mycard board above, it is a complete functional unit by itself, so it can be used as a module on any other board.

Maximum ROM size 512KByte (32x16K).
Attached to this post, board design files and PDF prints.

pinout.png (63.85 KB)

Module Pinout

mapper-module-v2.zip (186.59 KB)

SEGA Mapper clone

firmware.zip (1.14 KB)

GAL16V8 Firmware

Interesting, How spot on is the mapper? have you tested any official games with this design?

IllusionOfMana wrote

Interesting, How spot on is the mapper? have you tested any official games with this design?

It is a redesign of a previous project which had a working mapper. I made very minor changes, switched to CMOS (from TTL), used some SMD components and made it into a module on itself as not to depend on the SEGA card board. And of course, this time is legal for me to release it xD

So far I've successfuly tested:

- Sonic the hedgehog 2 (to completion)
- Bubble Bobble*
- Chuck Rock 2 (to completion)
- Ecco the Dolphin (Uses both SLOT1/2)

(*) Patched to work from Card Slot
So I'd say the design is solid enough.

How hard would it be to make it support up to 256 16KB banks (4 MB)?

I assume no SRAM support?

sverx wrote

How hard would it be to make it support up to 256 16KB banks (4 MB)?

* Finding a 4MB flash/EEPROM that can tolerate 5V
* Exposing the remaining 3 address/data pins (new PCB required, but same electronics)

IllusionOfMana wrote

I assume no SRAM support?

Not yet, but could be done.
Adding SRAM is bulky, will need extra work, and I don't currently have studied how SRAM works. Wasn't a priority.

NeonMan wrote

sverx wrote

How hard would it be to make it support up to 256 16KB banks (4 MB)?

* Finding a 4MB flash/EEPROM that can tolerate 5V

I wonder... is 512 KB the biggest? Anyway, what about having two chips on the PCB eventually?

There are a couple ways to get around the limits. Bigger ROMs, there are some TSSOP packages ones that tolerate 5V IIRC. you can also have multiple 512K ROMs and select each one with a muxer circuit (rather easy hack) or use bigger and wider ROMs (a 512KWord ROM at 16bit would yield 1MByte)

Neither would require significant mapper changes but would make the cartridge board significantly more complex/bigger.

Edit: The prototype cart on the 22nd anniversary post has 4 ROM chips and a suspiciously placed demuxer circuit (74HC157) so I'm guessing SEGA used this very same hack to "merge" multiple EPROMs. With up to a 1-to-8 demultiplexer you could manage a huge 8-ROM cartridge of 256x16K size.

coming back to this since the design for the mapper expansion board features multiple chips. Would it not be cheaper to just use a single micro controller or CPLD? That way if you ever wanted bigger rom or sram support, you shouldnt need a ton of extra components.

IllusionOfMana wrote

coming back to this since the design for the mapper expansion board features multiple chips. Would it not be cheaper to just use a single micro controller or CPLD? That way if you ever wanted bigger rom or sram support, you shouldnt need a ton of extra components.

I tried, just search PIC 18F44K22 on this forum, but a microcontroller is way too slow for this purpose, and 32bit micros (like the Teensy Boards) are even worse since interrupts and branches are slower per cycle, as far as I tried.

The instruction budget (talking from memory here) I had for a mapper, using the 18F series PIC micro was ~10/8 instructions total running the micro at a clock speed of 64Mhz and writing all the code in assembler. And I almost managed to make a SLOT2-Only mapper within that budget. SLOT1/2 was not doable and SLOT0 and SRAM were out of question.

I'm not saying is not doable using other micros, Cypress arm cores have a programmable logic cell like a CPLD and looked very promising, but regular CPLDs were a faster solution at a reasonable price point. More or less the price of a "beefy" 8-bit microcontroller, around $4 buying small quantities and PDIP for the PLDs, using all-SMD and buying bulk would be cheaper.

Using a single CPLD would probably be cheaper, even when 16v8 GALs are pretty cheap. Main reason I'm using that one is my programmer accepts them and the package (PDIP/SOIC) I easy to solder unlike the Altera MAX devices (everdrive uses these one IIRC) which I considered using at some point, are also cheap but not easy to solder by the average hobbist. After all, tradeoffs were made and, since the PLD firmware source code will be released soon, anyone can adapt the design eventually :)

Boards arrived and im missing just one component. However, here's the current aspect. ROM on black board, mapper on green board.

the card half has been tested and it works. Mapper testing will proceed when I get the 40pin connector I'm missing on the pic. And once is all tested, release the firmware source with it.

card-comparison.jpg (131.16 KB)

card

All components arrived, assembled the cartridges and tested the PLD "firmware" to confirm all is good. Since it is working and passing all tests, I have released the full design, boards and firmware, on my repository under open source licenses.

https://bitbucket.org/Heavydeck/sega-flash-card-v2/src/default/

Attached some pictures of the finished product. This revision of the mapper has a slight desing flaw, fixed by soldering an SMD resistor, but it has been fixed on the repository.

000.jpg (317.18 KB)

Card working on the console.

001.jpg (338.07 KB)

Finished boards, with game ROMs.

002.jpg (96.34 KB)

Hardware fix for V2.0, fixed on V2.1

exciting! love seeing your progress! Whats the max supported rom size?

The mapper as designed can do up to the 4MB maximum but as implemented on this board is limited to 512KB. You could do a new board with the same components, route the missing address lines and have a working 8MB cartridge.

Mapper capabilities on SLOT1 and SLOT2; SLOT0 is fixed.

NeonMan wrote

The mapper as designed can do up to the 8MB but as implemented on this board is limited to 512KB.

Mapper capabilities on SLOT1 and SLOT2; SLOT0 is fixed.

love it! I have been in debate of putting my project on a card or cart given that it doesn't require save and is pretty small at 256k. Never swap slot 0 anyways so it seems good!

If you only do SLOT2 banking you can remove one of the 8-bit latches, also, if your ROM is 256KB or less you can use the (usually) cheaper 4-bit latch 74HC173.

circuitry is the same for Cartridges and cards, mind you.

Correction: MAX is 4MB, not 8.

I ordered boards and will give this a try when they arrive, now I have a question. What is stopping me from using the M0-7 line on the card connector as a stand in for the A15 address line? If I understand correctly it is active low when the Z80 is accessing the first 32KB of the address space and high when it's not, Is there a technical reason why that M0-7 line can't drive a ROM or RAM chip address input or a mapper chip?

For a bit of background I wish to use the card slot for a mapped battery backed SRAM card that can be used in conjunction with a cart. With the different software selectable chip selects for each interface the card, cart and expansion ports can all be accessed independently so even without a mapper chip the SMS should be able to access 192KB of SRAM if your willing to disable the onboard RAM.

N2 wrote

so even without a mapper chip the SMS should be able to access 192KB of SRAM if you're willing to disable the onboard RAM.

Why stop there? Once you assume the software is writing to port $3E to swap between cart and card, why not also swap between those and the system RAM?

If you're intending mark 3 compatibility, to get programmatic control of card vs cart you'll need to add a latch - and then you may as well also choose to drive /DSRAM.

Quote

What is stopping me from using the M0-7 line on the card connector as a stand in for the A15 address line?

/M0-7 combines the MREQ signal with A15; nothing comes to mind as a reason why this wouldn't work.

Where can I source a replacement or equivalent card slot?

Can the state of the IOReq line be determined from the signals on the Card socket?

NeonMan wrote

All components arrived, assembled the cartridges and tested the PLD "firmware" to confirm all is good. Since it is working and passing all tests, I have released the full design, boards and firmware, on my repository under open source licenses.

https://bitbucket.org/Heavydeck/sega-flash-card-v2/src/default/

Attached some pictures of the finished product. This revision of the mapper has a slight desing flaw, fixed by soldering an SMD resistor, but it has been fixed on the repository.

Certainly /RD or /WR will only be low if either /MREQ or /IORQ are low, so if you see /MREQ high and /RD or /WR low, you can probably assume it's an I/O cycle ... timing might be rough, however.

I presume I'd have to figure out how to load the latch at $3E without the use of a chip enable from the interface it' connected too as those are controlled by the output of the Memory Control Register/Latch. This will also be increasingly interesting on the Card as the IORequest signal is lacking.

lidnariq wrote

N2 wrote

so even without a mapper chip the SMS should be able to access 192KB of SRAM if you're willing to disable the onboard RAM.

Why stop there? Once you assume the software is writing to port $3E to swap between cart and card, why not also swap between those and the system RAM?

If you're intending mark 3 compatibility, to get programmatic control of card vs cart you'll need to add a latch - and then you may as well also choose to drive /DSRAM.

Quote

What is stopping me from using the M0-7 line on the card connector as a stand in for the A15 address line?

/M0-7 combines the MREQ signal with A15; nothing comes to mind as a reason why this wouldn't work.

Author	Message
NeonMan Joined: 24 Sep 2013 Posts: 141	Making a SEGA card and mapper (this time fully open) Posted: Thu Jun 27, 2019 9:34 am Last edited by NeonMan on Thu Jul 25, 2019 12:12 am; edited 2 times in total
NeonMan Joined: 24 Sep 2013 Posts: 141	*Edit: Design finished, built and tested. Get the board design and firmware here* Two years ago I made a SEGA card clone with a mapper clone made out of discrete components, the bad part is that I made it with a not-really-legally-licensed and proprietary CAD solution (Proteus) and would put in trouble other people if I released it as is, so this time I'm fixing some issues it had, moving the mapper connector to a single 40pin header as to allow development of Hardware, and using KiCAD instead of any proprietary solution. I would like some feedback on this part of the circuit, which should work as a plain 32K cartridge, especially the ROM #CE line, which I'm not really sure if that's the correct way to use it, even though "it works" on the current revision of the board, and the chosen board dimensions, which are slightly smaller (a few dozen Thou narrower) since current board revision "scratches" the SMS port sides, board thickness increased from 1.6mm (which barely works) to 2mm (closer to real card thickness) The mapper will attach to the pin header, and will be released in a similar fashion later on this same thread. Separating it makes the boards cheaper to manufacture and allows the card port to be used as a general purpose peripheral port. Note that, with no mapper attached, you can put 5 jumpers between pins 32 to 40 and 31 to 39 to set ROM upper address to Zero and ROM A14 to Z80 A14, giving 32K of address space. Attached to this message are design files and PDF prints of them. Feedback welcome! :) sega_flash_card_v2.zip (170.94 KB)

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Fri Jun 28, 2019 4:53 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	Mapper module ready for use. No more need for "Donnor Cartridges" or FPGAs. At least for SLOT1/2 games. Also, while intended to be used with the SEGA mycard board above, it is a complete functional unit by itself, so it can be used as a module on any other board. Maximum ROM size 512KByte (32x16K). Attached to this post, board design files and PDF prints. pinout.png (63.85 KB) Module Pinout mapper-module-v2.zip (186.59 KB) SEGA Mapper clone firmware.zip (1.14 KB) GAL16V8 Firmware

IllusionOfMana Joined: 08 Sep 2018 Posts: 270	Posted: Fri Jun 28, 2019 6:18 pm
IllusionOfMana Joined: 08 Sep 2018 Posts: 270	Interesting, How spot on is the mapper? have you tested any official games with this design?

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Fri Jun 28, 2019 7:44 pm Last edited by NeonMan on Fri Jun 28, 2019 8:05 pm; edited 1 time in total
NeonMan Joined: 24 Sep 2013 Posts: 141	IllusionOfMana wrote Interesting, How spot on is the mapper? have you tested any official games with this design? It is a redesign of a previous project which had a working mapper. I made very minor changes, switched to CMOS (from TTL), used some SMD components and made it into a module on itself as not to depend on the SEGA card board. And of course, this time is legal for me to release it xD So far I've successfuly tested: - Sonic the hedgehog 2 (to completion) - Bubble Bobble* - Chuck Rock 2 (to completion) - Ecco the Dolphin (Uses both SLOT1/2) (*) Patched to work from Card Slot So I'd say the design is solid enough.

sverx Joined: 05 Sep 2013 Posts: 3996 Location: Stockholm, Sweden	Posted: Fri Jun 28, 2019 7:59 pm
	How hard would it be to make it support up to 256 16KB banks (4 MB)?

IllusionOfMana Joined: 08 Sep 2018 Posts: 270	Posted: Fri Jun 28, 2019 8:05 pm
IllusionOfMana Joined: 08 Sep 2018 Posts: 270	I assume no SRAM support?

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Fri Jun 28, 2019 8:07 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	sverx wrote How hard would it be to make it support up to 256 16KB banks (4 MB)? * Finding a 4MB flash/EEPROM that can tolerate 5V * Exposing the remaining 3 address/data pins (new PCB required, but same electronics)

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Fri Jun 28, 2019 8:09 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	IllusionOfMana wrote I assume no SRAM support? Not yet, but could be done. Adding SRAM is bulky, will need extra work, and I don't currently have studied how SRAM works. Wasn't a priority.

sverx Joined: 05 Sep 2013 Posts: 3996 Location: Stockholm, Sweden	Posted: Sat Jun 29, 2019 10:29 am
	NeonMan wrote sverx wrote How hard would it be to make it support up to 256 16KB banks (4 MB)? * Finding a 4MB flash/EEPROM that can tolerate 5V I wonder... is 512 KB the biggest? Anyway, what about having two chips on the PCB eventually?

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Sat Jun 29, 2019 2:09 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	There are a couple ways to get around the limits. Bigger ROMs, there are some TSSOP packages ones that tolerate 5V IIRC. you can also have multiple 512K ROMs and select each one with a muxer circuit (rather easy hack) or use bigger and wider ROMs (a 512KWord ROM at 16bit would yield 1MByte) Neither would require significant mapper changes but would make the cartridge board significantly more complex/bigger. Edit: The prototype cart on the 22nd anniversary post has 4 ROM chips and a suspiciously placed demuxer circuit (74HC157) so I'm guessing SEGA used this very same hack to "merge" multiple EPROMs. With up to a 1-to-8 demultiplexer you could manage a huge 8-ROM cartridge of 256x16K size.

IllusionOfMana Joined: 08 Sep 2018 Posts: 270	Posted: Sun Jun 30, 2019 5:35 pm
IllusionOfMana Joined: 08 Sep 2018 Posts: 270	coming back to this since the design for the mapper expansion board features multiple chips. Would it not be cheaper to just use a single micro controller or CPLD? That way if you ever wanted bigger rom or sram support, you shouldnt need a ton of extra components.

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Sun Jun 30, 2019 7:02 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	IllusionOfMana wrote coming back to this since the design for the mapper expansion board features multiple chips. Would it not be cheaper to just use a single micro controller or CPLD? That way if you ever wanted bigger rom or sram support, you shouldnt need a ton of extra components. I tried, just search PIC 18F44K22 on this forum, but a microcontroller is way too slow for this purpose, and 32bit micros (like the Teensy Boards) are even worse since interrupts and branches are slower per cycle, as far as I tried. The instruction budget (talking from memory here) I had for a mapper, using the 18F series PIC micro was ~10/8 instructions total running the micro at a clock speed of 64Mhz and writing all the code in assembler. And I almost managed to make a SLOT2-Only mapper within that budget. SLOT1/2 was not doable and SLOT0 and SRAM were out of question. I'm not saying is not doable using other micros, Cypress arm cores have a programmable logic cell like a CPLD and looked very promising, but regular CPLDs were a faster solution at a reasonable price point. More or less the price of a "beefy" 8-bit microcontroller, around $4 buying small quantities and PDIP for the PLDs, using all-SMD and buying bulk would be cheaper. Using a single CPLD would probably be cheaper, even when 16v8 GALs are pretty cheap. Main reason I'm using that one is my programmer accepts them and the package (PDIP/SOIC) I easy to solder unlike the Altera MAX devices (everdrive uses these one IIRC) which I considered using at some point, are also cheap but not easy to solder by the average hobbist. After all, tradeoffs were made and, since the PLD firmware source code will be released soon, anyone can adapt the design eventually :)

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Wed Jul 17, 2019 4:39 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	Boards arrived and im missing just one component. However, here's the current aspect. ROM on black board, mapper on green board. the card half has been tested and it works. Mapper testing will proceed when I get the 40pin connector I'm missing on the pic. And once is all tested, release the firmware source with it. card-comparison.jpg (131.16 KB) card

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Tue Jul 23, 2019 11:00 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	All components arrived, assembled the cartridges and tested the PLD "firmware" to confirm all is good. Since it is working and passing all tests, I have released the full design, boards and firmware, on my repository under open source licenses. https://bitbucket.org/Heavydeck/sega-flash-card-v2/src/default/ Attached some pictures of the finished product. This revision of the mapper has a slight desing flaw, fixed by soldering an SMD resistor, but it has been fixed on the repository. 000.jpg (317.18 KB) Card working on the console. 001.jpg (338.07 KB) Finished boards, with game ROMs. 002.jpg (96.34 KB) Hardware fix for V2.0, fixed on V2.1

IllusionOfMana Joined: 08 Sep 2018 Posts: 270	Posted: Wed Jul 24, 2019 10:44 pm
IllusionOfMana Joined: 08 Sep 2018 Posts: 270	exciting! love seeing your progress! Whats the max supported rom size?

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Wed Jul 24, 2019 11:52 pm Last edited by NeonMan on Wed Jul 24, 2019 11:56 pm; edited 1 time in total
NeonMan Joined: 24 Sep 2013 Posts: 141	The mapper as designed can do up to the 4MB maximum but as implemented on this board is limited to 512KB. You could do a new board with the same components, route the missing address lines and have a working 8MB cartridge. Mapper capabilities on SLOT1 and SLOT2; SLOT0 is fixed.

IllusionOfMana Joined: 08 Sep 2018 Posts: 270	Posted: Wed Jul 24, 2019 11:55 pm
IllusionOfMana Joined: 08 Sep 2018 Posts: 270	NeonMan wrote The mapper as designed can do up to the 8MB but as implemented on this board is limited to 512KB. Mapper capabilities on SLOT1 and SLOT2; SLOT0 is fixed. love it! I have been in debate of putting my project on a card or cart given that it doesn't require save and is pretty small at 256k. Never swap slot 0 anyways so it seems good!

NeonMan Joined: 24 Sep 2013 Posts: 141	Posted: Wed Jul 24, 2019 11:58 pm
NeonMan Joined: 24 Sep 2013 Posts: 141	If you only do SLOT2 banking you can remove one of the 8-bit latches, also, if your ROM is 256KB or less you can use the (usually) cheaper 4-bit latch 74HC173. circuitry is the same for Cartridges and cards, mind you. Correction: MAX is 4MB, not 8.

N2 Joined: 13 Oct 2023 Posts: 7	SEGA adapter Posted: Sun Dec 08, 2024 8:51 pm
N2 Joined: 13 Oct 2023 Posts: 7	I ordered boards and will give this a try when they arrive, now I have a question. What is stopping me from using the M0-7 line on the card connector as a stand in for the A15 address line? If I understand correctly it is active low when the Z80 is accessing the first 32KB of the address space and high when it's not, Is there a technical reason why that M0-7 line can't drive a ROM or RAM chip address input or a mapper chip? For a bit of background I wish to use the card slot for a mapped battery backed SRAM card that can be used in conjunction with a cart. With the different software selectable chip selects for each interface the card, cart and expansion ports can all be accessed independently so even without a mapper chip the SMS should be able to access 192KB of SRAM if your willing to disable the onboard RAM.

lidnariq Joined: 24 Mar 2021 Posts: 148	Posted: Mon Dec 09, 2024 8:07 am
lidnariq Joined: 24 Mar 2021 Posts: 148	N2 wrote so even without a mapper chip the SMS should be able to access 192KB of SRAM if you're willing to disable the onboard RAM. Why stop there? Once you assume the software is writing to port $3E to swap between cart and card, why not also swap between those and the system RAM? If you're intending mark 3 compatibility, to get programmatic control of card vs cart you'll need to add a latch - and then you may as well also choose to drive /DSRAM. Quote What is stopping me from using the M0-7 line on the card connector as a stand in for the A15 address line? /M0-7 combines the MREQ signal with A15; nothing comes to mind as a reason why this wouldn't work.

N2 Joined: 13 Oct 2023 Posts: 7	Posted: Tue Dec 17, 2024 3:55 pm
N2 Joined: 13 Oct 2023 Posts: 7	Where can I source a replacement or equivalent card slot?

N2 Joined: 13 Oct 2023 Posts: 7	How can I create the IOReq signal? Posted: Tue Dec 24, 2024 1:26 am
N2 Joined: 13 Oct 2023 Posts: 7	Can the state of the IOReq line be determined from the signals on the Card socket? NeonMan wrote All components arrived, assembled the cartridges and tested the PLD "firmware" to confirm all is good. Since it is working and passing all tests, I have released the full design, boards and firmware, on my repository under open source licenses. https://bitbucket.org/Heavydeck/sega-flash-card-v2/src/default/ Attached some pictures of the finished product. This revision of the mapper has a slight desing flaw, fixed by soldering an SMD resistor, but it has been fixed on the repository.

lidnariq Joined: 24 Mar 2021 Posts: 148	Posted: Tue Dec 24, 2024 2:58 pm
lidnariq Joined: 24 Mar 2021 Posts: 148	Certainly /RD or /WR will only be low if either /MREQ or /IORQ are low, so if you see /MREQ high and /RD or /WR low, you can probably assume it's an I/O cycle ... timing might be rough, however.

N2 Joined: 13 Oct 2023 Posts: 7	Posted: Wed Dec 25, 2024 3:03 am
N2 Joined: 13 Oct 2023 Posts: 7	I presume I'd have to figure out how to load the latch at $3E without the use of a chip enable from the interface it' connected too as those are controlled by the output of the Memory Control Register/Latch. This will also be increasingly interesting on the Card as the IORequest signal is lacking. lidnariq wrote N2 wrote so even without a mapper chip the SMS should be able to access 192KB of SRAM if you're willing to disable the onboard RAM. Why stop there? Once you assume the software is writing to port $3E to swap between cart and card, why not also swap between those and the system RAM? If you're intending mark 3 compatibility, to get programmatic control of card vs cart you'll need to add a latch - and then you may as well also choose to drive /DSRAM. Quote What is stopping me from using the M0-7 line on the card connector as a stand in for the A15 address line? /M0-7 combines the MREQ signal with A15; nothing comes to mind as a reason why this wouldn't work.

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