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- Joined: 23 Nov 2016
- Posts: 16
- Location: Argentina
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LDIR timing on MEKA
Posted: Tue Dec 13, 2016 7:42 pm
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Hi,
I'm trying to understand a behaviour on the instruction LDIR on MEKA.
I'm debugging for example, Ghost House, and on PC = 0x88, it hits LDIR.
Now, after finishing it, sometimes the lines counter finishes on 230 lines, and sometimes on 228. The inputs are always the same, since it's just resetting ram. Shouldn't it always take the same amount of time ?
According to online documentation, it takes 21 cycles if BC != 0, otherwise 16
Thanks,
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- Site Admin
- Joined: 19 Oct 1999
- Posts: 14756
- Location: London
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Posted: Tue Dec 13, 2016 11:09 pm
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Is bc the same every time? Are the start points the same each time? Is the interrupt firing on line 192 (or whatever it is, I'm not sure) or is it delayed due to disabled interrupts?
Meka does have some faulty timing on some of the extended opcodes, but I found that via the CLOCK cycle counter, not the line counter.
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- Joined: 23 Nov 2016
- Posts: 16
- Location: Argentina
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Posted: Wed Dec 14, 2016 1:57 am
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All registers are the same every time, the instruction is hit almost at the start of the program, interrupts are always disabled.
So, MEKA has some kind of random duration for LDIR ?
Can anyone confirm this ?
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- Site Admin
- Joined: 19 Oct 1999
- Posts: 14756
- Location: London
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Posted: Wed Dec 14, 2016 5:54 am
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What's the code path to offset $88? I'd assumed it was in the VBlank, are you saying it's at startup? I think Meka is deterministic, if sometimes inaccurate.
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- Joined: 23 Nov 2016
- Posts: 16
- Location: Argentina
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Posted: Wed Dec 14, 2016 1:11 pm
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Cycles are always correct until just before LDIR.
After LDIR is random
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- Joined: 08 Dec 2005
- Posts: 488
- Location: Melbourne, Australia
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Posted: Thu Dec 15, 2016 7:11 am
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I only see line 230. Are you clicking "Reset Emulation" before each run?
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- Joined: 23 Nov 2016
- Posts: 16
- Location: Argentina
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Posted: Thu Dec 15, 2016 1:11 pm
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I hit reload ROM, which seems to reset every counter.
Check the IPeriod value, it's always different, even if the lines are 230
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- Site Admin
- Joined: 19 Oct 1999
- Posts: 14756
- Location: London
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Posted: Thu Dec 15, 2016 8:27 pm
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It seems to be consistent for me. I load the ROM (the export version), then "c 88" gets me to line 0 iperiod 85, and then "s" gets me to line 25 iperiod 85. I do a ctrl+backspace hard reset to try again. CLOCK says 184977 cycles every time. (The ldir in question is blanking all of RAM at startup, which is why it's only 85 cycles into the execution, and interrupts are not up yet.)
Edit: I am using a version of latest Github Meka with altered cycle timings, which I think are more correct (Meka's seem to include wait states for some rarely used opcodes, which is wrong) so you may find your clock count is higher, but this has no effect on the consistency.
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- Site Admin
- Joined: 08 Jul 2001
- Posts: 8661
- Location: Paris, France
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Posted: Fri Dec 16, 2016 8:46 am
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Which version of MEKA are you using?
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