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View topic - 315-5297 (and more Japanese MS stuff) pinout

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  • Joined: 06 Feb 2009
  • Posts: 110
  • Location: Toulouse, France
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315-5297 (and more Japanese MS stuff) pinout
Post Posted: Wed Nov 26, 2014 2:20 pm
Some time ago I started studying the Japanese Master System board scans available here as an exercise to figure the pinout of 315-5297 I/O chip.

I took some time to finish it recently and completed it with pinouts for the rest of the chips, maybe this could be interesting or useful to someone.

----------------------------------------------------------------------------
 I/O Controller: 315-5297
----------------------------------------------------------------------------

                        +----v----+
                 Z80 A0 |1  i s 64| Vcc
                 Z80 A1 |2  i o 63| LED
                 Z80 A2 |3  i ? 62| /CONT2 ? (N/C)
                 Z80 A3 |4  i i 61| /CONT1 (connected to CONT pin on CN2/CN3/CN4)
                 Z80 A4 |5  i i 60| AUTO (connected to AUTO SW)
                 Z80 A5 |6  i i 59| KILLRAM (CN3 pin B3 only, with pull-down resistor)
                 Z80 A6 |7  i o 58| /CE2 (CN2 pin 13)
                 Z80 A7 |8  i o 57| /CE3 (CN3 pin B10)
                 Z80 A8 |9  i o 56| /CE4 (CN4 pin 13)
                 Z80 A9 |10 i o 55| /CE0 (RAM /CE pin) ?
                Z80 A10 |11 i o 54| /CE1 (ROM /CE pin) ?
                Z80 A11 |12 i b 53| 2TR
                Z80 A12 |13 i i 52| 2RI
                Z80 A13 |14 i i 51| 2LE
                Z80 A14 |15 i i 50| 2DW
                Z80 A15 |16 i i 49| 2UP
             /RESET_OUT |17 o i 48| 2TL
   (CN4 pin 43) KILLJOY |18 i b 47| 2TH (with pull-up RC)
              /RESET_IN |19 i b 46| 1TR
              Z80 /RD ? |20 i i 45| 1RI
              Z80 /WR ? |21 i i 44| 1LE
              Z80 /MREQ |22 i i 43| 1DW
           Z80 /IOREQ ? |23 i i 42| 1UP
                 Z80 D0 |24 b i 41| 1TL
                 Z80 D1 |25 b b 40| 1TH (with pull-up resistor)
                 Z80 D2 |26 b o 39| /HL ?
                 Z80 D3 |27 b o 38| /FM_CS (YM2413 pin 12) ?
                 Z80 D4 |28 b o 37| FM_ENABLE (74HC4066 pin 12) ?
                 Z80 D5 |29 b o 36| PSG_ENABLE (74HC4066 pin 6) ?
                 Z80 D6 |30 b o 35| 3D_LR (BA10324 pin 2 & pin 9)
                 Z80 D7 |31 b o 34| 3D_REF (BA10324 pin 6)
                    GND |32 s o 33| 3D_ON (BA10324 pin 4 with voltage multiplier circuitry)
                        +---------+


Pins marked with '?' are not 100% verified (signals function should be correct but exact position within a group of signals could not be confimed, only guessed from visible tracks).



Notes :
-------

(1) I/O chip decodes full Z80 address range and does not use /KBSEL (neither /CSRAM) generated by VDP, which means:
.I/O ports are likely not mirrored in whole $00-$3F range as with SG-1000, Mark-III and export Master System
so it should not be necessary to disable I/O ports before accessing FM chip (Japanese BIOS doesn't)
.I/O and memory control registers (ports $3E and $3F) are likely not mirrored in whole $00-$3F range as with
export Master System

(2) TH pins are connected to I/O ports (CN5 & CN6) pin 7 and port $3H is used to configure TH & TR pins as inputs
or outputs but according to Enri's website, reading TH bit only returns the current i/o state (0 for an output
and 1 for an input). That's said, it could be that:
. when set as an output, the written value is correctly output to the controller port but not buffered in I/O chip (returning 0 when read)
. when set as an input, it correctly returns the state of the TH pin from the controller (which would be 1 if left unconnected as with gamepads).

This means that contrary to Mark-III console, peripherals using this pin (export Sports Pad & Paddle, 3-Buttons & 6 Buttons controller, Light Gun) might still be compatible ?

(3) /RESET_IN comes from POWER SW and /RESET_OUT goes to Z80, VDP, YM2413, CN3 and CN4 /RESET pins

(4) LED is controlled by I/O chip (maybe it can be enabled/disabled from software through unused port in $00-$3F or $C0-$FF range ?)

(5) FM & PSG analog outputs are controlled by I/O chip through a 74HC40066 analog switch (cf. pin analysis below):
.Japanese BIOS enables both by writing $03 to port $F2
.Mark-III softwares enable (resp. disable) FM output by writing $01 (resp. $00) to port $F2

(6) 3D Glasses are controlled by I/O chip through a BA10324 analog amplifier connected to a 3-wire jack plug (cf. pin analysis below)


----------------------------------------------------------------------------
 VDP : 315-5124 (copied from m3tech.txt)
----------------------------------------------------------------------------

                        +----v----+
                 Z80 D0 |01 b o 64| Z80 /INT
                 Z80 D1 |02 b i 63| Z80 A7
                 Z80 D2 |03 b i 62| Z80 A6
                 Z80 D3 |04 b i 61| Z80 A0
                 Z80 D4 |05 b i 60| Z80 /IORQ
                 Z80 D5 |06 b i 59| Z80 /WR
                 Z80 D6 |07 b i 58| Z80 /RD
                 Z80 D7 |08 b i 57| /NTSC (PAL)
                    GND |09 s b 56| VRAM AD15
                  AUDIO |10 o b 55| VRAM AD14
                    Vcc |11 s b 54| VRAM AD13
                     TO |12 o b 53| VRAM AD12
                     TI |13 i b 52| VRAM AD11
                 /KBSEL |14 o b 51| VRAM AD10
                 /CSRAM |15 o b 50| VRAM AD9
                  /EXM1 |16 o b 49| VRAM AD8
                  /EXM2 |17 o b 48| VRAM AD7
                Z80 A14 |18 i b 47| VRAM AD6
                Z80 A15 |19 i b 46| VRAM AD5
              Z80 /MREQ |20 i b 45| VRAM AD4
               Z80 /NMI |21 o b 44| VRAM AD3
                /NMI-IN |22 i b 43| VRAM AD2
                 /RESET |23 i b 42| VRAM AD1
                   /CBT |24 o b 41| VRAM AD0
                   /PCP |25 o s 40| Vcc
                R-VIDEO |26 o o 39| VRAM /CE
                G-VIDEO |27 o o 38| VRAM /WE1
                B-VIDEO |28 o o 37| VRAM /WE0
                /C-SYNC |29 o o 36| VRAM /OE
                  XTAL1 |30 i i 35| /H-L
                  XTAL2 |31 o o 34| Z80 /CLK
                    GND |32 s o 33| Y1
                        +---------+


Pins 12 (TO), 24 (/CBT), 25 (/PCP) & 33 (Y1) are not connected
Pins 13 (TI) and 57 (/NTSC) are connected to GND


----------------------------------------------------------------------------
 Analog Amplifier: BA10324
----------------------------------------------------------------------------

                        +----v----+
       (CN8 pin 1) OUT1 |1  o o 14| OUT4 (N/C)
           (GND ?) IN1- |2  i i 13| IN4- (GND)
 (315-5997 pin 35) IN1+ |3  i i 12| IN4+ (Vcc)
  (Vcc multiplier)   V+ |4  s s 11| V-   (GND)
           (GND ?) IN2+ |5  i i 10| IN3+ (GND ?)
 (315-5997 pin 34) IN2- |6  i i  9| IN3- (315-5997 pin 35)
       (CN8 pin 4) OUT2 |7  o o  8| OUT3 (CN8 pin 2)
                        +---------+


pins 2 (IN1-), 5 (IN2+) & 10 (IN3+) seems logically connected to GND but, for some unknown reason, the signal is coming from the audio/video circuit and is also connected to CA358E pins 3 & 5 (INA- & INB-) and CXA1145 pin 14 (Vref)

pin 1 (OUT1) & pin 8 (OUT3) are inverted outputs connected resp. to CN8 pin 1 (orange cable) & pin 2 (yellow cable) going to 171-5542 (3D) board
-> 315-5997 pin 35 connected to pin 3 (IN1+) & pin 9 (IN3-) is used to control left/right 3D glass selection (either as stereo or balanced mono signals)

pin 7 (OUT2) is connected to CN8 pin 4 (black cable) going to 171-5542 (3D) board
-> 315-5997 pin 34 connected to pin 6 (IN2-) is used to control 3D glasses common (ref) signal

pin 4 (V+) is connected to a voltage multiplier circuit (Vcc/5V -> 12V ?) & 315-5997 pin 33
-> 315-5997 pin 33 is used to power on/off 3D glasses


The voltage multiplier & jack amplifier circuit seems similar (but not exactly the same) as the one used in Mark-III 3D card adapter (cf. Enri's website)


----------------------------------------------------------------------------
 FM Synthetizer: YM2413
----------------------------------------------------------------------------

                        +----v----+
                    GND |1  s i 18| Z80 D1
                 Z80 D2 |2  i i 17| Z80 D0
                 Z80 D3 |3  i s 16| Vcc
                 Z80 D4 |4  i o 15| RO (mixed to CA358E pin 2)
                 Z80 D5 |5  i o 14| MO (mixed to CA358E pin 2)
                 Z80 D6 |6  i i 13| /RESET (from 315-5297)
                 Z80 D7 |7  i i 12| /FM_CS (from 315-5297)
               Z80 /CLK |8  i i 11| /Z80_WR
              (N/C) XIN |9  o i 10| Z80 A0
                        +---------+




----------------------------------------------------------------------------
 Audio Switch: 74HC4066
----------------------------------------------------------------------------

                        +----v----+
               (GND) 1Y |1  b s 14| Vcc
               (GND) 1Z |2  b b 13| 1E (GND)
               (GND) 2Z |3  b b 12| 4E / FM_ENABLE
               (GND) 2Y |4  b o 11| 4Y / FM_OUT  (mixed to CA358E pin 6)
               (GND) 2E |5  b i 10| 4Z / FM_IN   (from CA358E pin 1)
        PSG_ENABLE / 3E |6  b i  9| 3Z / PSG_IN  (from VDP pin 10)
                    GND |7  s o  8| 3Y / PSG_OUT (mixed to CA358E pin 6)
                        +---------+




----------------------------------------------------------------------------
 Audio Amplifier: CA358E
----------------------------------------------------------------------------

                        +----v----+
 (74HC4066 pin 10) OUTA |1  o s  8| V+   (Vcc)
(YM2413 pin 14&15) INA+ |2  i o  7| OUTB (CXA1145 pin 8)
           (GND ?) INA- |3  i i  6| INB+ (74HC4066 pin 8&11)
             (GND)   V- |4  s i  5| INB- (GND ?)
                        +---------+




----------------------------------------------------------------------------
 Video Encoder: CXA1145
----------------------------------------------------------------------------

                        +----v----+
                    GND |1  s o 24| GND
   (VDP pin 26) R_VIDEO |2  i i 23| R_OUT (CN1 pin 6)
   (VDP pin 27) G_VIDEO |3  i i 22| G_OUT (CN1 pin 5)
   (VDP pin 28) B_VIDEO |4  i i 21| B_OUT (CN1 pin 8)
             (N/C) XOUT |5  b i 20| VIDEO_OUT (CN1 pin 3)
         (Z80 /CLK) XIN |6  b i 19| Vcc
             (Vcc) NTSC |7  b i 18| Y_IN  (Y_OUT)
(CA358E pin 7) AUDIO_IN |8  b i 17| C_IN  (C_OUT)
  (CN1 pin 1) AUDIO_OUT |9  s b 16| Y_OUT (Y_IN)
  (VDP pin 29) CSYNC_IN |10 o b 15| C_OUT (C_IN)
  (CN1 pin 7) CSYNC_OUT |11 s b 14| Vref (GND ?)
                    Vcc |12 o b 13| Iref (GND ?)
                        +---------+




----------------------------------------------------------------------------
 A/V connector (CN1):
----------------------------------------------------------------------------


                         7            6
                                8
                       3                1

                         5            4
                                2
1: AUDIO
2: GND
3: VIDEO
4: Vcc
5: G
6: R
7: CSYNC
8: B




----------------------------------------------------------------------------
 Card connector (CN2):
----------------------------------------------------------------------------

                         _______
                        |        \
                    Vcc |1  s i  2| Z80 /WR
              Z80 /MREQ |3  i i  4| Z80 /RD
                  /EXM1 |5  i i  6| Z80 A14
                Z80 A13 |7  i i  8| Z80 A8
                 Z80 A9 |9  i i 10| Z80 A11
                  /EXM2 |11 i i 12| Z80 A10
                   /CE2 |13 i b 14| Z80 D7
                 Z80 D6 |15 b b 16| Z80 D5
                 Z80 D4 |17 b b 18| Z80 D3
                    GND |19 s s 20| GND
                    GND |21 s b 22| Z80 D2
                 Z80 D1 |23 b b 24| Z80 D0
                 Z80 A0 |25 i i 26| Z80 A1
                 Z80 A2 |27 i i 28| Z80 A3
                 Z80 A4 |29 i i 30| Z80 A5
                 Z80 A6 |31 i i 32| Z80 A7
                Z80 A12 |33 i o 34| /CONT
                    Vcc |35 s    /
                        +-------+



Pinout is identical to export Master System card connector.

Compatibility with Mark-III cards is maintained, the only differences being that:

. pin 3 (/CSRAM on Mark-III) is connected to Z80 /MREQ
. pin 13 (Z80 /MREQ + /CARD input from cartridge port pin B2 on Mark-III) is connected to 315-5297 /CE2 pin (card /CE)

Pin B2 on cartridge port which was used to disable or enable the card port from hardware on Mark-III is not used here and card port is now only controllable by software. It might be possible to use a second pair of 3D-Glasses with Mark-III card adapter if card port is enabled through port $3E.


----------------------------------------------------------------------------
 Cartridge connector (CN3):
----------------------------------------------------------------------------

                       +-----------+
                Z80 A0 |A1  i s  B1| Vcc
                Z80 A1 |A2  i s  B2| Vcc
                Z80 A2 |A3  i o  B3| KILLRAM (->pull-down)
                Z80 A3 |A4  i i  B4| /EXM1
                Z80 A4 |A5  i i  B5| Z80 /RD
                Z80 A5 |A6  i i  B6| Z80 /WR
                Z80 A6 |A7  i i  B7| /RESET ?
                Z80 A7 |A8  i -  B8| N/C
                Z80 A8 |A9  i i  B9| Z80 /MREQ
                Z80 A9 |A10 i i B10| /CE3
               Z80 A10 |A11 i o B11| /CONT
               Z80 A11 |A12 i - B12| N/C
               Z80 A12 |A13 i - B13| N/C
               Z80 A13 |A14 i - B14| N/C
                Z80 D0 |A15 b - B15| N/C
                Z80 D1 |A16 b - B16| N/C
                Z80 D2 |A17 b - B17| N/C
                Z80 D3 |A18 b i B18| Z80 A14
                Z80 D4 |A19 b i B19| /EXM2
                Z80 D5 |A20 b - B20| N/C
                Z80 D6 |A21 b s B21| GND
                Z80 D7 |A22 b s B22| GND
                       +-----------+



Pinout is identical to SG-1000 & Mark-III cartridge connector except that:

. pin B2 (/CARD on Mark-III only) is connected to Vcc

. pin B3 (/CSRAM on Mark-III & SG-1000) is not directly connected with VDP /CSRAM pin or RAM /CE but to 315-5297 pin 57 (with pull-down resistor) instead, which still allows to disable internal RAM from cartridge hardware.

. pin B7 (N/C on Mark-III & SG-1000) is connected to 315-5297 /RESET_OUT pin (not confirmed)

. pin B9 (N/C on Mark-III & SG-1000) is connected to Z80 /MREQ

. pin B10 (Z80 /MREQ on Mark-III and SG-1000) is connected to 315-5297 /CE3 pin (cartridge /CE), controlled from software (BIOS), but is also connected to /EXM2 pin on CN2/CN3/CN4 through diode D2 (so cartridge is enabled by default in $0000-$8000 if /CE3 pin is left floating)


----------------------------------------------------------------------------
 Expansion connector (CN4):
----------------------------------------------------------------------------

                        +---------+
                    Vcc |1  s i  2| Z80 /WR
              Z80 /MREQ |3  i i  4| Z80 /RD
                  /EXM1 |5  i i  6| Z80 A14
                Z80 A13 |7  i i  8| Z80 A8
                 Z80 A9 |9  i i 10| Z80 A11
                  /EXM2 |11 i i 12| Z80 A10
                   /CE4 |13 i b 14| Z80 D7
                 Z80 D6 |15 b b 16| Z80 D5
                 Z80 D4 |17 b b 18| Z80 D3
                    GND |19 s s 20| GND
                    GND |21 s b 22| Z80 D2
                 Z80 D1 |23 b b 24| Z80 D0
                 Z80 A0 |25 i i 26| Z80 A1
                 Z80 A2 |27 i i 28| Z80 A3
                 Z80 A4 |29 i i 30| Z80 A5
                 Z80 A6 |31 i i 32| Z80 A7
                Z80 A12 |33 i o 34| /CONT
                    Vcc |35 s i 36| Z80 A15
              Z80 /M1 ? |37 i i 38| Z80 /IOREQ ?
            Z80 /RFSH ? |39 i i 40| Z80 /HALT ?
(->pull-up) Z80 /WAIT ? |41 o i 42| Z80 /INT ?
              KILLJOY ? |43 o o 44| Z80 /BUSREQ ? (->pull-up)
          Z80 /BUSACK ? |45 i i 46| /RESET ?
              Z80 CLK ? |47 i i 48| /KBSEL ?
                 /CSRAM |49 i i 50| /NMI-IN
                        +---------+

Pins marked with '?' could not be confirmed.



Pinout seems identical to export Master System expansion connector and is not compatible with SG-1000 or Mark-III peripherals.
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Post Posted: Wed Nov 26, 2014 3:47 pm
Thank you for your work!
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Post Posted: Wed Nov 26, 2014 6:21 pm
You're welcome to post this on our wiki too...
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