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I was just reading heliophobes source code to one of his programs and something I read triggered something in my brain. I remember reading the old docs like Jons and remember James McKay saying to only write to vram addresses >0x4000 to <0x7fff . In helio's source he says that he sets the addresses to 0x4000 to start writing and clears vram till 0x7fff. What im thinking is maybe that you arent really writing to addresses 0x4000-0x7fff, just you have to set bit 15 to write to vram, and you have to clear it to read from vram. IF anyone can point out some obvious thing I am missing out then please do so, I just thought it was an interesting little thing ;).

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> I was just reading heliophobes source code to one of his programs and something I read triggered something in my brain. I remember reading the old docs like Jons and remember James McKay saying to only write to vram addresses >0x4000 to <0x7fff . In helio's source he says that he sets the addresses to 0x4000 to start writing and clears vram till 0x7fff. What im thinking is maybe that you arent really writing to addresses 0x4000-0x7fff, just you have to set bit 15 to write to vram, and you have to clear it to read from vram. IF anyone can point out some obvious thing I am missing out then please do so, I just thought it was an interesting little thing ;).

Yeah, it's better explain in Charles somethingorother's VDP doc, but:

There's 16k of VRAM. Thus, it's a 14-bit addressable space. When sending bytes to the VDP address port ($bf), the top two bits of the two-byte sequence sent to it have the following meaning:

00 - Set the VDP to address specified in the other 14 bits, in read mode.
01 - Set the VDP to address specified in the other 14 bits, in write mode.
10 - Write to a VDP register: the first 8 bits sent are the value to write, bits 8-11 are the VDP register #. (bits 12 and 13 are probably ignored, but I don't know this for certain).
11 - Set the VDP to write the the palette registers (not really part of video ram). bits 0-4 select which palette to write to, the other bits are probably masked (ignored). There's no way to read the palette registers (so I've heard).

You could just as well look at it that $0-$3fff and $4000-$7fff are mirrors to eachother, one in read mode and one in write, but the above explaination more accurately reflects the actual behavior of the VDP.
I guess.

Yah i know the stuff abuot the command bits in the second byte from Charles doc. What do you think happens when a read is requested when its 01, and a write when its 00? Do you think they are ignored or do you not know? Just curious is all ;).
-Jason Starr-

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> Yah i know the stuff abuot the command bits in the second byte from Charles doc. What do you think happens when a read is requested when its 01, and a write when its 00? Do you think they are ignored or do you not know? Just curious is all ;).

I think this comes back to what was said in one of the docs (Jon's?) about throwing away the first byte read (which you'd need to do if reading in write mode, as the data in the latch will be invalid). Setting read mode supposedly has the effect of automatically loading the latch with the byte from the address specified and incrementing the address counter, or something like that (from the 9918 doc).

So it should be possible to do reads in "write" mode and vice versa; how you set the control bits just affects the initial behaviour. Perhaps you could use this to do both read and write operations on contiguous sections of VRAM, without needing to change the control bits. Maybe.

Mike

Why did James McKay implecitly tell Zoop and SMSC to only write to $4000 - $7FFF then? Just curious as he seems adamant about that. And if it was possible to write with command bits being 00, why does he say not to? Weird hey :)
-Jason Starr-

i think JM is right, after all the Z80 accesses VRAM through the VDP. the command bit in question tells the VDP whether to (1) transfer the data from the CPU interface latches to VRAM on the next free memory cycle or (2) transfer data from VRAM to the CPU interface latches. All the CPU does is write to or read the latches, nothing more.

...it makes sense to me anyways.

a s out.

Author	Message
PolestaR Guest	SMs coding Stuff Posted: Wed Feb 28, 2001 4:16 am
PolestaR Guest	I was just reading heliophobes source code to one of his programs and something I read triggered something in my brain. I remember reading the old docs like Jons and remember James McKay saying to only write to vram addresses >0x4000 to <0x7fff . In helio's source he says that he sets the addresses to 0x4000 to start writing and clears vram till 0x7fff. What im thinking is maybe that you arent really writing to addresses 0x4000-0x7fff, just you have to set bit 15 to write to vram, and you have to clear it to read from vram. IF anyone can point out some obvious thing I am missing out then please do so, I just thought it was an interesting little thing ;).

Heliophobe Site Admin Joined: 25 Oct 1999 Posts: 2029 Location: Monterey, California	Posted: Wed Feb 28, 2001 4:37 am
	Quote > I was just reading heliophobes source code to one of his programs and something I read triggered something in my brain. I remember reading the old docs like Jons and remember James McKay saying to only write to vram addresses >0x4000 to <0x7fff . In helio's source he says that he sets the addresses to 0x4000 to start writing and clears vram till 0x7fff. What im thinking is maybe that you arent really writing to addresses 0x4000-0x7fff, just you have to set bit 15 to write to vram, and you have to clear it to read from vram. IF anyone can point out some obvious thing I am missing out then please do so, I just thought it was an interesting little thing ;). Yeah, it's better explain in Charles somethingorother's VDP doc, but: There's 16k of VRAM. Thus, it's a 14-bit addressable space. When sending bytes to the VDP address port ($bf), the top two bits of the two-byte sequence sent to it have the following meaning: 00 - Set the VDP to address specified in the other 14 bits, in read mode. 01 - Set the VDP to address specified in the other 14 bits, in write mode. 10 - Write to a VDP register: the first 8 bits sent are the value to write, bits 8-11 are the VDP register #. (bits 12 and 13 are probably ignored, but I don't know this for certain). 11 - Set the VDP to write the the palette registers (not really part of video ram). bits 0-4 select which palette to write to, the other bits are probably masked (ignored). There's no way to read the palette registers (so I've heard). You could just as well look at it that $0-$3fff and $4000-$7fff are mirrors to eachother, one in read mode and one in write, but the above explaination more accurately reflects the actual behavior of the VDP. I guess.

PolestaR Guest	Posted: Wed Feb 28, 2001 5:41 am
PolestaR Guest	Yah i know the stuff abuot the command bits in the second byte from Charles doc. What do you think happens when a read is requested when its 01, and a write when its 00? Do you think they are ignored or do you not know? Just curious is all ;). -Jason Starr-

Mike G Joined: 21 Apr 2000 Posts: 598 Location: Newcastle upon Tyne, England	Posted: Wed Feb 28, 2001 7:17 am
	Quote > Yah i know the stuff abuot the command bits in the second byte from Charles doc. What do you think happens when a read is requested when its 01, and a write when its 00? Do you think they are ignored or do you not know? Just curious is all ;). I think this comes back to what was said in one of the docs (Jon's?) about throwing away the first byte read (which you'd need to do if reading in write mode, as the data in the latch will be invalid). Setting read mode supposedly has the effect of automatically loading the latch with the byte from the address specified and incrementing the address counter, or something like that (from the 9918 doc). So it should be possible to do reads in "write" mode and vice versa; how you set the control bits just affects the initial behaviour. Perhaps you could use this to do both read and write operations on contiguous sections of VRAM, without needing to change the control bits. Maybe. Mike

PolestaR Guest	Posted: Wed Feb 28, 2001 7:23 am
PolestaR Guest	Why did James McKay implecitly tell Zoop and SMSC to only write to $4000 - $7FFF then? Just curious as he seems adamant about that. And if it was possible to write with command bits being 00, why does he say not to? Weird hey :) -Jason Starr-

asynchronous Joined: 14 Aug 2000 Posts: 742 Location: Adelaide, Australia	Re: VDP command bits Posted: Fri Mar 02, 2001 4:49 am
	i think JM is right, after all the Z80 accesses VRAM through the VDP. the command bit in question tells the VDP whether to (1) transfer the data from the CPU interface latches to VRAM on the next free memory cycle or (2) transfer data from VRAM to the CPU interface latches. All the CPU does is write to or read the latches, nothing more. ...it makes sense to me anyways. a s out.

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