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Game Gear TV Tuner and LCD Protocol DecodingPosted: Wed Aug 25, 2021 1:52 pm
Last edited by thatawesomeguy on Thu Oct 13, 2022 6:28 am; edited 3 times in total
I've wanted to better document the Game Gear TV Tuner protocol for a while but didn't have the means to do so until recently.
I've been capturing the signals from the 19 pins used by the tuner accessory with a logic analyzer to get a better understanding.
Charles MacDonald already has some documentation up on the wiki at:
I have found however some differences in timing between what he observed and what I've observed, though I'm far less knowledgable in how to interpret the data I've captured, and may take me some time..
If you wish to view the capture data you can download the software here:
||Posted: Thu Aug 26, 2021 9:51 pm|
Sure there could have been some errors in my measurements. There's also at least two TV tuner types (analog tuning vs digital tuning) and it's possible combinations of different tuners and GGs (1 ASIC vs 2 ASIC vs other types) have inconsistent timing.
Ideally on the tuner page we should have PCB photos of the different types and look for some labels to distinguish them. If we keep the different GG and tuner types in mind, we can probably figure out if there's measurement errors or actual differences between test setups.
||Posted: Thu Aug 26, 2021 11:21 pm|
|I don't have any single asic Game Gears, but I do have both versions of the tuner so I can check.|
||Posted: Thu Sep 16, 2021 9:00 am|
What started as an investigation into the TV Tuner has become a deep dive into the operation of the Game Gear LCD as they are functionally equivalent.
The LCD has 160x146 pixels. The Game Gear VDP has a native NTSC resolution of 256x192 pixels with a window of 160x144 pixels visible at any one time, the discrepancy between the VDP vertical resolution and the LCD is accounted for by the fact that 1 pixel of the VDP is represented by a 2x1 pixel on the LCD at half brightness, it unknown if this is intentional or a flaw, it results in an image that is less sharp than its source material.
The display is driven by three ICs using Chip On Glass technology. Each chip has two clock lines that operate 1/3 of the display each with a shared data bus.
The pixel clock is divided into 6 channels labeled CLA1, CLA2, CLA3, CLB1, CLB2, CLB3 respectively (CL1A1, CL1A2, CL1A3, CL1B1, CL1B2, CL1B3 on the TV Tuner but can be used interchangeably). Each channel is clocked 80 times in turn to equal 480 clocks per scanline. Every three clock pulses form one pixel represented as an RGB 12 bit value (4:4:4) on D01-D04. 480 / 3 = 160 pixels per scanline, exactly the horizontal resolution of the LCD.
The clock lines are paired CLB1/CLA1, CLB2/CLA2, CLB3/CLA3 respectively, all the CLB clocks are responsible for odd sub-pixels and CLA clocks are responsible for the even sub-pixels, alternating between the two as the row is drawn.
The CLA/B pairs are the same clock with one channel inverted, data is read from D01-D04 on the falling edge of each pulse. This has the effect of interleaving the RGB data between each clock pair.
DW is the Vertical Sync signal and indicates the start and end of 1 frame.
CL2 is the Horizontal Sync and indicates the start of a new scanline.
TPR1 and TPR2 have an unknown function, they go to a separate part of the display responsible for contrast control. In native Game Gear mode and when using the NTSC TV Tuner they are inverted signals that occur around the same time as VSYNC, with the PAL TV Tuner TPR2 is held high while TPR1 pulses outside the VSYNC period just before the first pixel clock.
P1-P4 is a 4 bit ripple counter that sometimes counts up and other times counts down. DB seems to follow each full cycle of the counter and is shown grouped together in the service manual.
In NTSC mode it counts down from 0xF to 0x0 with DB alternating each cycle, sometimes DB will alternate after two cycles instead of one.
With the PAL TV Tuner this counter alternates counting from 0x1 to 0xF and from 0x1 to 0xF each frame.
The pixel clock and data format also differ slightly on the PAL TV Tuner. The encoding scheme is the same, however, the timing is different whereby some frames will clock CLB1-CLB3 followed by CLA1-CLA3 and other frames they will be in the reverse order, this does not affect the relationship between the clock line and the sub-pixel mapping.
When the TV Tuner is in operation the crystal oscillator on the mainboard is shut off and the signals are routed from the cartridge connector to the LCD via the SCA, there's no direct electrical connection..