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View topic - Behaviour for invalid VDP access sequences

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Behaviour for invalid VDP access sequences
Post Posted: Wed Jul 15, 2020 8:44 pm
I'm just writing my first VDP emulation attempt, albeit one that only tries to emulate the VRAM, no rendering. Reading Charles' doc, I've implemented the address and control registers, and the read buffer. The logical conclusion of the doc is that if I were to have this sequence:

Control port: write 0x12, 0x88
Data port: write 0xff

The first two bytes would be setting VDP register 8 (X scroll) to value 0x12, but would also leave the address register at 0x0812. The third write would then set the contents of VRAM address 0x0812 and increment the address register to 0x813.

Is this correct? Does anything actually rely on this? The doc doesn't actually mention this specific "invalid" sequence.

Also, what's the power-on value of the registers and read buffer contents?
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Post Posted: Thu Jul 16, 2020 2:57 pm
I believe the first write is setting the low part of the address, not sure if the second write affects the high part at all. But I never investigated that.
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Post Posted: Thu Jul 16, 2020 8:06 pm
I guess I ought to make a test for it...
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Post Posted: Thu Jul 16, 2020 8:26 pm
I read that again now, it seems you're likely right

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When the first byte is written, the lower 8 bits of the address register are updated. When the second byte is written, the upper 6 bits of the address register and the code register are updated, and the VDP may carry out additional processing based on the value of the code register


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VDP register write
While the address and code register are updated like normal when a VDP register write is done, the ...
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Post Posted: Fri Jul 17, 2020 6:55 am
Yes, that does seem to cover it. I’m curious if anything depends on it.
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