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  • Joined: 25 Feb 2013
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  • Location: Osaka
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SG-1000 NMI
Post Posted: Wed Jun 17, 2020 1:15 am
I was looking at this schematic of the sg-1000 here and I do not understand the circuit controlling the NMI.

When pin 11 of IC13 goes low (IO to the PSG), NMI is the transistor's Vbe + R4/ (R4+R5+R6) = about Vbe, which may trigger NMI. clearly this is not the intended behavior.

Is the schematic wrong? or am I wrong? I do not get the intent of the circuitry either. I guess something like not allowing NMI while the psg is enabled? and what about M1?
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