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View topic - GG vdp in master system + Custom IO Chip

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  • Joined: 05 Nov 2014
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GG vdp in master system + Custom IO Chip
Post Posted: Fri Apr 10, 2020 7:02 am
Last edited by wasup on Yesterday at 3:57 am; edited 1 time in total
Just had a bit of a thought but not sure if it would work in practice. Would it be possible to take the vdp and vram from a 2 asic game gear and transplant that into a master system? Had a quick look at the VA0 schematic and it looks doable in terms of required pins. Obviously the sound and video outputs are going to be different. A GGTV board should sort the video out. Not sure about the sound.. there appears to be 4 output pins involved with that, but would imagine its not too difficult to sort out. Im not sure how the vdp knows which mode to operate in (gg vs sms) as that seems to be fed into the other asic but there are some pins between the two that may be used for that. Has this been tried before or can any one see why it might not work?
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Post Posted: Fri Apr 10, 2020 8:02 am
I guess it depends what is in which chip, I don’t think we’ve given it much thought. If it is doing the VDP + VRAM + LCD driver then it seems plausible. It might take some unknown funky signals from the other ASIC though.
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Post Posted: Fri Apr 10, 2020 8:12 am
On the diagram i found it seems to be separate z80 + external ram, vdp in one asic + external vram then IO + lcd driver + sound related in the second asic.

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Post Posted: Fri Apr 10, 2020 10:33 am
well, you might do a 'consolized' Game Gear and add a port for SMS games...
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Post Posted: Fri Apr 10, 2020 10:53 am
sverx wrote
well, you might do a 'consolized' Game Gear and add a port for SMS games...


There is that.. but theres no TH pin on port 1 so controller support becomes limited. Hacking in an sms io chip might be doable as well tho
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Post Posted: Mon May 04, 2020 3:41 pm
wasup wrote
sverx wrote
well, you might do a 'consolized' Game Gear and add a port for SMS games...


There is that.. but theres no TH pin on port 1 so controller support becomes limited. Hacking in an sms io chip might be doable as well tho


Lookup "neto"s posts on here. EDIT, see here:
https://www.smspower.org/forums/16031-GameGearLightPhaserAndSoftReset#98444

Neto is an 8 bit Sega god much like yourself, who developed an add on circuit like your 3D board that adds TH pins to both ports :)

I think you can do absolutely everything with a consolized GG...only 2 games need patching for FM but I think thats it (if you use available circuits).
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Post Posted: Sun May 31, 2020 5:56 am
Im gona have a look at making my own mod to add full support for th and tr (as both inputs and outputs) for p1 and p2. Then all controllers will be fully supported. The only issue will be the pause/start button.. as decoding a megadrive controller then breaks the port compatability with th and tr.
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Post Posted: Mon Jun 01, 2020 3:07 am
wasup wrote
Im gona have a look at making my own mod to add full support for th and tr (as both inputs and outputs) for p1 and p2. Then all controllers will be fully supported. The only issue will be the pause/start button.. as decoding a megadrive controller then breaks the port compatability with th and tr.


Lmk if you want to work together on this. Ive already made a decoding board for the MD controller and you can mux pin 7 (clk or th) to make it compatible.
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Post Posted: Yesterday at 4:17 am
I had a quick play in PSoC creater (the software for Cypress PSoC chips) and the basics of an IO chip should be straight forward to do in the programmable logic portion of a chip. I don't think the TH output for the VDP is quite right.. might need an and gate instead, but the general idea is there. Running outs of IO pins on the chips i have but i could probably just go for a bigger one and drop in 3D glasses support and decoding for a megadrive controller too. A software driven config menu might make it a bit nicer than having external switches to set options. Then we can also set the stack pointer as well as set palette data for SG-1000 games.
IO.PNG (77.2 KB)
IO.PNG

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Post Posted: Yesterday at 4:20 am
having this all in a CPLD would be incredible

bows down to the master
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GG vdp in master system + Custom IO Chip
Post Posted: Yesterday at 1:01 pm
It's totally doable. I drew up a gate schematic of IC4 a while back. I think I just had the POR to do when something more important popped up.

Although I'm not sure what you mean by "megadrive controller decoding"?

I might have to check out this CAD tool. And here I was about to read up on VHDL!
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Post Posted: Today at 2:59 am
asynchronous wrote
Although I'm not sure what you mean by "megadrive controller decoding"


Just driving a megadrive/genesis controller from the micro to be able to be able to read the start button. It breaks compatability with other controller tho.. so im thinking of having that switchable.
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