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Here's a mostly complete 315-5246 pinout. This is heavily based on information asynchronous and Marty had posted before (thanks!), with a few additions from myself:

Edit: Made some additions on 10/24/2013 now that we have the SMS 2 Service Manual.

+----v----+
Z80 D0 |01 b o 64| Z80 /INT
Z80 D1 |02 b i 63| Z80 A7
Z80 D2 |03 b i 62| Z80 A6
Z80 D3 |04 b i 61| Z80 A0
Z80 D4 |05 b i 60| Z80 /IORQ
Z80 D5 |06 b i 59| Z80 /WR
Z80 D6 |07 b i 58| Z80 /RD
Z80 D7 |08 b i 57| PAL//NTSC
/KBSEL |09 o b 56| VRAM AD15
/CSRAM |10 o b 55| VRAM AD14
/EXM1 |11 o b 54| VRAM AD13
/EXM2 |12 o b 53| VRAM AD12
Z80 A14 |13 i b 52| VRAM AD11
TI |14 i b 51| VRAM AD10
AUDIO |15 o b 50| VRAM AD9
TO |16 o b 49| VRAM AD8
GND |17 s b 48| VRAM AD7
+5V |18 s b 47| VRAM AD6
Z80 A15 |19 i b 46| VRAM AD5
Z80 /MREQ |20 i b 45| VRAM AD4
Z80 /NMI |21 o b 44| VRAM AD3
/NMI-IN |22 i b 43| VRAM AD2
Z80 /RST |23 i b 42| VRAM AD1
/H-L |24 i b 41| VRAM AD0
/CBT |25 o s 40| +5V
HI-OUT |26 i o 39| VRAM /CE
R-VIDEO |27 o o 38| VRAM /OE
G-VIDEO |28 o o 37| VRAM /WE0
B-VIDEO |29 o o 36| VRAM /WE1
/C-SYNC |30 o i 35| XIN
/YS |31 o o 34| XOUT
GND |32 s o 33| Z80 /CLK
+---------+

/YS goes low for transparent pixels, high for opaque pixels. If the border color is zero, it goes low during the border areas too, colors $01-$0F are treated as opaque.

/CBT goes low during the front porch for 2.607 uS for what I assume is the color burst. This would allow 9.3 cycles of a 3.58 MHz clock to be inserted into the video output by external hardware.

XIN can be connected to a TTL oscillator (leave XOUT open) or a crystal.

/H-L latches the H counter on a high to low transition. The H counter remains latched until the next high to low transition. Normally the I/O chip drives this pin.

HI-OUT affects the RGB output levels. I don't think it's actually a reference signal as all consoles have it grounded and the MegaPlay arcade board has it set to +5V, but just another input you tie high or low. In a console, if it's pulled high all colors are heavily saturated towards white.

TO is a test pin output. It is usually left open or connected to ground through a capacitor in the 270pF range.

TI is a test pin input. It is always grounded.

Configurations that I know of:

Mega Play
Pin 14 (TI) = Ground
Pin 16 (TO) = Open
Pin 26 (HI-OUT) = +5V

NTSC SMS 2
Pin 14 (TI) = Ground
Pin 16 (TO) = Open
Pin 26 (HI-OUT) = Ground

PAL SMS 2 (thanks NFG)
Pin 14 (TI) = Ground
Pin 16 (TO) = Through capacitor C25 to ground
Pin 26 (HI-OUT) = Ground

And here's the 315-5330 pinout:

+----v----+
GND |01 s s 42| +5V
VRAM AD15 |02 i o 41| SRAM /WE
VRAM AD14 |03 i o 40| SRAM A12
VRAM AD13 |04 i o 39| SRAM A13
VRAM AD12 |05 i o 38| SRAM A8
VRAM AD11 |06 i o 37| SRAM A9
VRAM AD10 |07 i o 36| SRAM A11
VRAM AD9 |08 i o 35| SRAM /OE
VRAM AD8 |09 i o 34| SRAM A10
VRAM AD7 |10 i o 33| SRAM D7
GND |11 s s 32| GND
VRAM AD6 |12 i i 31| VRAM AD1
VRAM AD5 |13 i o 30| SRAM D6
VRAM AD4 |14 i i 29| VRAM AD0
VRAM AD3 |15 i o 28| SRAM D5
VRAM AD2 |16 i o 27| SRAM D0
VRAM /CE |17 i o 26| SRAM D4
VRAM /OE |18 i o 25| SRAM D1
VRAM /WE0 |19 i o 24| SRAM D3
VRAM /WE1 |20 i o 23| SRAM D2
+5V |21 s s 22| GND
+---------+

This is found in some consoles, it interfaces a single SRAM to the VDP instead of two PSRAMs. Funny thing is, I don't see how it could work as it doesn't hold the address on SRAM A7-A0, those are directly connected to VRAM AD7-AD0.

SRAM connections:

A15 = GND (only first 16K of 32K available)
SRAM D0-D7 from 315-5330
SRAM A13-A8 from 315-5330
SRAM A7-A0 from 315-5246 AD0-AD7
SRAM /CE from 315-5246 VRAM /CE

Nice work as usual Charles. “You are great” – Cloud Master

Going by track thickness I’d say that pin 17 is Vss. I initially thought that pin 16 may be an audio signal ground and likewise pin 26 to be an RGB signal ground.

From my own electronic draft notes my PAL SMS2 has
Pin 14 = N.C,
Pin 16 = ground,
Pin 26 = ground.

I may have to double-check pin 14 - it may be connected to ground through a capacitor which would be an open circuit in a continuity test. The VDP page of my SMS2 schematics that I drew up in 2001 has gone missing (mild panic!) so I’ll have to open the console up to check at some point.

Some integrated circuits with analog sections have pins which allow a capacitor to be externally connected for signal filtering, e.g. a low pass filter to filter out any high frequency noise introduced from digital sections, but I’m not sure if this is the case here. Hmmm…

Asynchronous.

Charles MacDonald wrote

Funny thing is, I don't see how it could work as it doesn't hold the address on SRAM A7-A0, those are directly connected to VRAM AD7-AD0.

I know this is a very old thread but I just wanted to share the fact the address latching is done by the PSRAM itself when CE goes low (it's in the documentation).

Also a couple of years ago I reproduced that 315-5330 custom chip with TTL chips, it wasn't overly complicated but I've lost any track of my work...

https://www.arcade-projects.com/threads/solved-help-me-revive-a-sega-mega-play-p...

I guess it shouldn't be too complicated to recreate it once again (IIRC there was only a few chips, two LS245s used to select where to redirect D0~7 from the PSRAM to either A0~7 or A8~15 of the VDP, one LS08 for some signal combinations like PSRAM WE = WE0 & WE1, one LS32 for the bus direction of the LS245s combining control signals, etc.).

Author	Message
Charles MacDonald Joined: 28 Sep 1999 Posts: 1200	315-5246 and 315-5330 pinouts Posted: Fri Jun 29, 2007 5:54 am Last edited by Charles MacDonald on Fri Oct 25, 2013 12:08 am; edited 2 times in total
Charles MacDonald Joined: 28 Sep 1999 Posts: 1200	Here's a mostly complete 315-5246 pinout. This is heavily based on information asynchronous and Marty had posted before (thanks!), with a few additions from myself: Edit: Made some additions on 10/24/2013 now that we have the SMS 2 Service Manual. +----v----+ Z80 D0 \|01 b o 64\| Z80 /INT Z80 D1 \|02 b i 63\| Z80 A7 Z80 D2 \|03 b i 62\| Z80 A6 Z80 D3 \|04 b i 61\| Z80 A0 Z80 D4 \|05 b i 60\| Z80 /IORQ Z80 D5 \|06 b i 59\| Z80 /WR Z80 D6 \|07 b i 58\| Z80 /RD Z80 D7 \|08 b i 57\| PAL//NTSC /KBSEL \|09 o b 56\| VRAM AD15 /CSRAM \|10 o b 55\| VRAM AD14 /EXM1 \|11 o b 54\| VRAM AD13 /EXM2 \|12 o b 53\| VRAM AD12 Z80 A14 \|13 i b 52\| VRAM AD11 TI \|14 i b 51\| VRAM AD10 AUDIO \|15 o b 50\| VRAM AD9 TO \|16 o b 49\| VRAM AD8 GND \|17 s b 48\| VRAM AD7 +5V \|18 s b 47\| VRAM AD6 Z80 A15 \|19 i b 46\| VRAM AD5 Z80 /MREQ \|20 i b 45\| VRAM AD4 Z80 /NMI \|21 o b 44\| VRAM AD3 /NMI-IN \|22 i b 43\| VRAM AD2 Z80 /RST \|23 i b 42\| VRAM AD1 /H-L \|24 i b 41\| VRAM AD0 /CBT \|25 o s 40\| +5V HI-OUT \|26 i o 39\| VRAM /CE R-VIDEO \|27 o o 38\| VRAM /OE G-VIDEO \|28 o o 37\| VRAM /WE0 B-VIDEO \|29 o o 36\| VRAM /WE1 /C-SYNC \|30 o i 35\| XIN /YS \|31 o o 34\| XOUT GND \|32 s o 33\| Z80 /CLK +---------+ /YS goes low for transparent pixels, high for opaque pixels. If the border color is zero, it goes low during the border areas too, colors $01-$0F are treated as opaque. /CBT goes low during the front porch for 2.607 uS for what I assume is the color burst. This would allow 9.3 cycles of a 3.58 MHz clock to be inserted into the video output by external hardware. XIN can be connected to a TTL oscillator (leave XOUT open) or a crystal. /H-L latches the H counter on a high to low transition. The H counter remains latched until the next high to low transition. Normally the I/O chip drives this pin. HI-OUT affects the RGB output levels. I don't think it's actually a reference signal as all consoles have it grounded and the MegaPlay arcade board has it set to +5V, but just another input you tie high or low. In a console, if it's pulled high all colors are heavily saturated towards white. TO is a test pin output. It is usually left open or connected to ground through a capacitor in the 270pF range. TI is a test pin input. It is always grounded. Configurations that I know of: Mega Play Pin 14 (TI) = Ground Pin 16 (TO) = Open Pin 26 (HI-OUT) = +5V NTSC SMS 2 Pin 14 (TI) = Ground Pin 16 (TO) = Open Pin 26 (HI-OUT) = Ground PAL SMS 2 (thanks NFG) Pin 14 (TI) = Ground Pin 16 (TO) = Through capacitor C25 to ground Pin 26 (HI-OUT) = Ground And here's the 315-5330 pinout: +----v----+ GND \|01 s s 42\| +5V VRAM AD15 \|02 i o 41\| SRAM /WE VRAM AD14 \|03 i o 40\| SRAM A12 VRAM AD13 \|04 i o 39\| SRAM A13 VRAM AD12 \|05 i o 38\| SRAM A8 VRAM AD11 \|06 i o 37\| SRAM A9 VRAM AD10 \|07 i o 36\| SRAM A11 VRAM AD9 \|08 i o 35\| SRAM /OE VRAM AD8 \|09 i o 34\| SRAM A10 VRAM AD7 \|10 i o 33\| SRAM D7 GND \|11 s s 32\| GND VRAM AD6 \|12 i i 31\| VRAM AD1 VRAM AD5 \|13 i o 30\| SRAM D6 VRAM AD4 \|14 i i 29\| VRAM AD0 VRAM AD3 \|15 i o 28\| SRAM D5 VRAM AD2 \|16 i o 27\| SRAM D0 VRAM /CE \|17 i o 26\| SRAM D4 VRAM /OE \|18 i o 25\| SRAM D1 VRAM /WE0 \|19 i o 24\| SRAM D3 VRAM /WE1 \|20 i o 23\| SRAM D2 +5V \|21 s s 22\| GND +---------+ This is found in some consoles, it interfaces a single SRAM to the VDP instead of two PSRAMs. Funny thing is, I don't see how it could work as it doesn't hold the address on SRAM A7-A0, those are directly connected to VRAM AD7-AD0. SRAM connections: A15 = GND (only first 16K of 32K available) SRAM D0-D7 from 315-5330 SRAM A13-A8 from 315-5330 SRAM A7-A0 from 315-5246 AD0-AD7 SRAM /CE from 315-5246 VRAM /CE

asynchronous Joined: 14 Aug 2000 Posts: 764 Location: Adelaide, Australia	315-5246 and 315-5330 pinouts Posted: Thu Jul 05, 2007 4:19 pm
	Nice work as usual Charles. “You are great” – Cloud Master Going by track thickness I’d say that pin 17 is Vss. I initially thought that pin 16 may be an audio signal ground and likewise pin 26 to be an RGB signal ground. From my own electronic draft notes my PAL SMS2 has Pin 14 = N.C, Pin 16 = ground, Pin 26 = ground. I may have to double-check pin 14 - it may be connected to ground through a capacitor which would be an open circuit in a continuity test. The VDP page of my SMS2 schematics that I drew up in 2001 has gone missing (mild panic!) so I’ll have to open the console up to check at some point. Some integrated circuits with analog sections have pins which allow a capacitor to be externally connected for signal filtering, e.g. a low pass filter to filter out any high frequency noise introduced from digital sections, but I’m not sure if this is the case here. Hmmm… Asynchronous.

Apocalypse Joined: 26 Feb 2021 Posts: 163	Posted: Sun Jan 30, 2022 9:20 am
Apocalypse Joined: 26 Feb 2021 Posts: 163	Charles MacDonald wrote Funny thing is, I don't see how it could work as it doesn't hold the address on SRAM A7-A0, those are directly connected to VRAM AD7-AD0. I know this is a very old thread but I just wanted to share the fact the address latching is done by the PSRAM itself when CE goes low (it's in the documentation). Also a couple of years ago I reproduced that 315-5330 custom chip with TTL chips, it wasn't overly complicated but I've lost any track of my work... https://www.arcade-projects.com/threads/solved-help-me-revive-a-sega-mega-play-p... I guess it shouldn't be too complicated to recreate it once again (IIRC there was only a few chips, two LS245s used to select where to redirect D0~7 from the PSRAM to either A0~7 or A8~15 of the VDP, one LS08 for some signal combinations like PSRAM WE = WE0 & WE1, one LS32 for the bus direction of the LS245s combining control signals, etc.).

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