Overview

The registers of the VDP chip are used to control its operation.

Registers $00 and $01 control basic functions of the VDP.

Registers $02 to $06 are used to define the lead address of various tables stored in VRAM. The size of these tables are different between the TMS9918 and SMS display modes, so as a result not all of the bits in a bitfield of a particular register are used the same way between modes. Some address bits are taken into account differently by the VDP in Mode 4 when generating addresses for reading table data. Conceptually you can think of the bit being an input to a logic gate gate where the other input is a VRAM address bus bit. On the SMS1 VDP, this gate is like an AND; If the bit is set to 1, the output follows the input. Otherwise the output is forced to 0 at all times; Because of this behaviour, they are referred to as 'mask' bits. On the SMS2 VDP, the gate always gets a 1 from the register, so no addresses get masked off.

Registers $07 to $0A are used for various extensions to the TMS9918a chip upon which the VDP is based.

Register $00 - Mode Control No. 1

BitCodeFunction (SMS/GGFunction (TMS9918a)
7 Vertical scroll lockNo effect
6 Horizontal scroll lockNo effect
5 Hide leftmost 8 pixelsNo effect
4IE1Enable line interruptsNo effect
3ECShift sprites left 8 pixelsNo effect
2M4Mode 4 enableNo effect
1M2Extra height enable/TMS9918 mode selectSelect Graphics 2 mode
0 Sync disableEnable external video sync

Register $01 - Mode Control No. 2

BitCodeFunction (Mode 4)Function (TMS9918a modes)
7 No effectVRAM size select: 1 = 16KB, 0 = 4KB
6BLKEnable displayEnable display
5IE0Enable frame interruptsEnable frame interrupts
4M1224-line modeSelect Text mode
3M3240-line modeSelect Multicolor mode
2 No effectNo effect
1 Large (tiled, 8x16) spritesLarge (16x16) sprites
0 Doubled (stretched) spritesDoubled (stretched) sprites

Register $02 - Name Table Base Address

VDP typeBits
 76543210
TMS9918UnusedName table base address
SMS1UnusedName table base addressMask bit
SMS2/GGUnusedName table base addressUnused

Mode 4, 192-line display mode

If mode 4 is used in the 192-line display mode, the name table base address bits are combined with row/column coordinates to give the VRAM address of the specified name table entry:

 VRAM address bus layout for name table fetch
 MSB             LSB
 --bb byyy yyxx xxxw : b= Table base address, y= Row, x= Column
 ---- -x-- ---- ---- : x= Mask bit (bit 0 of register $02)

The mask bit is ANDed with the high bit of the y coordinate. This leads to tilemap mirroring with the SMS1 VDP.

In a math approach, bits 1-3 of this register are multiplied by $800 to get the base address - for example if bits 1-3 are all set, the address is 7 * $800 = $3800. For the majority of cases, all bits of this register may be set to 1 to give a name table at VRAM address $3800.

Mode 4, 224 and 240-line display modes

If Mode 4 is used in the 224 or 240-line display mode, only bits 3 and 2 are used to calculate the table address, and an offset of $700 is added to the address value:

Bit 3Bit2Address
00$0700
01$1700
10$2700
11$3700

In a math approach, bits 2-3 of this register are multiplied by $1000 to get the base address and then $700 is added to the total - for example if bits 2-3 are all set, the address is (3 * $1000) + $700 = $3700. For the majority of cases, all bits of this register may be set to 1 to give a name table at VRAM address $3700.

Register $03 - Color Table Base Address

This register defines the VRAM location of a table which defines foreground/background colours in some TMS9918a modes. For Mode 4 on the SMS1 VDP, all bits should be 1 to give normal operation.

VRAM address of the corresponding pattern generator (tile):

 VRAM address bus layout for tile pattern generator fetch
 MSB             LSB
 --nn nnnn nnny yypp : n= Tile number (0-511) y= Tile line, p= Bitplane select (0-3)
 --xx xxxx xx-- --0- : x= SMS1 Mask bits (bits 7-0 of register $03), only applied when pp={0,1}

Register $04 - Pattern Generator Table Base Address

This register defines the VRAM location of a table which defines patterns (tiles) in TMS9918a modes. For the SMS1 VDP, at least the low three bits should be 1 to give normal operation.

VRAM address of the corresponding pattern generator (tile):

 VRAM address bus layout for tile pattern generator fetch
 MSB             LSB
 --nn nnnn nnny yypp : n= Tile number (0-511) y= Tile line, p= Bitplane select (0-3)
 --xx x--- ---- --1- : x= SMS1 Mask bits (bits 2-0 of register $04), only applied when pp={2,3}

Register $05 - Sprite Attribute Table Base Address

VDP typeBits
 76543210
TMS9918UnusedSprite attribute table base address
SMS1UnusedSprite attribute table base addressMask bit
SMS2/GGUnusedSprite attribute table base addressUnused

In mode 4, the sprite attribute table base address bits are combined with the sprite number to give the VRAM address of a given sprite's attributes:

 VRAM address bus layout for sprite data fetches
 MSB             LSB
 --bb bbbb 00iii iii : y-coordinate      b= Table base
 --bb bbbb 1iii iii0 : x-coordinate      0/1 = Fixed '0' or '1' bit
 --bb bbbb 1iii iii1 : tile number       i= Sprite number (0-63)
 ---- ---- x--- ---- : Mask bit (bit 0 of register $05)

The mask bit is ANDed with the address; thus, the x-coordinates and tile numbers will incorrectly map to the first half of the sprite attribute table if the mask bit is 0. It should therefore always be set to 1.

For the majority of cases, all bits of this register may be set to 1 to give a sprite attribute table at VRAM address $3f00.

The possible addresses for the sprite attribute table occur every 256 bytes in VRAM, so it could be at an address like $0000, $0100, $0200 ... $3d00, $3e00, $3f00.

Register $06 - Sprite Pattern Generator Table Base Address

The register bits are:

VDP typeBits
 76543210
TMS9918UnusedSprite pattern generator table base address
SMS1UnusedSprite pattern generator table base addressMask bits
SMS2/GGUnusedSprite pattern generator table base addressUnused

In mode 4, the sprite pattern generator table base address bit is combined with a sprite's tile number to give the VRAM address of the corresponding pattern generator (tile):

 VRAM address bus layout for sprite pattern generator fetch
 MSB             LSB
 --bn nnnn nnny yypp : b= Table base address, n= Tile number (0-255) y= Tile line, p= Bitplane select (0-3)
 ---x x--- ---- ---- : x= Mask bits (bits 1,0 of register $06)

The mask bits are ANDed with the address, which will have the effect of restricting effective tile set from 255 down to 128 or 64 tiles accordingly. They should therefore always be set to 1.

As the sprite pattern generator table base address is determined by Bit 2, sprites can therefore use pattern graphics from either of these two addresses:

Bit 2Address
0$0000
1$2000

If Bit 2 is set and the start address is $2000, this also limits the numer of pattern tiles which can be used for sprites to 192 rather than 256, as the Name Table and Sprite Attribute Table usually occupy the upper part VRAM from $3800 onwards.

Register $07 - Overscan/Backdrop Color

In mode 4, this selects the colour to use for the backgrop/overscan area from the sprite palette. It is thus a 4-bit number, the upper 4 bits having no effect.

Register $08 - Background X Scroll

All eight bits define the horizontal scroll value.

Register $09 - Background Y Scroll

All eight bits define the vertical scroll value.

Register $0A - Line counter

All eight bits define the line counter value used for line interrupts.

Register $0B-$0F - no effect

The VDP is unaffected when register $0B and above are written to.

Miscellany

I recall register $03 and $02 had some other unusual side effects, such as disabling certain bitplanes from being shown. Register $03 affected the X/Y offsets into the name table so you could reduce the name table size from 32x32 down to smaller sizes like 16x16, 4x4, and even non-square dimensions too. Generally speaking register $04 did not function identically to $06 though you think they should. I'll get these tested at some point and update this section accordingly. - Charles MacDonald


References




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