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DevelopmentSega Master System / Mark III / Game Gear |
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The first revision for the PAL model 1. It is very similar to its NTSC counterpart, but has a clock divider circuit based around a 53.204 MHz crystal and discrete components. This clock divider is normally hidden underneath a small RF shield which is soldered to the board.
Most of these boards have the v1.3 BIOS, but a few have the v2.0 BIOS, which does not perform a header check.
Photos by Paul Baker, Mark Knibbs