Sega Master System and Game Gear Architecture version 1.0 [09/30/1996] by Marat Fayzullin [fms@freeflight.com] WWW: http://www.freeflight.com/fms/ IRC: RST38h The following document describes the hardware architecture of Sega Master System, also known as Mark3 in the East (Korea, Japan). It also covers the Sega GameGear, which is a later implementation of the same architecture. Note that this document is in no way based on any official Sega information and may be incomplete and incorrect in many places. "Sega Master System" and "GameGear" are registered trademarks of Sega. I would like to thank following people for their help in obtaining this information (sorted alphabetically): Richard Aplin Neil Harding Chris Shay The current version of this file is missing some information. I will add these parts in later releases. If you have any information on SMS/GG, which is not in this manual, feel free to write to fms@freeflight.com. Your help will be appreciated. ******************************* Contents ******************************* 1. General Architecture 2. I/O Ports 3. Joysticks 4. Nationalization 5. VDP a) VRAM b) Palette Registers c) Mode Registers d) Status Register e) Screen f) Sprites 6. Memory Mapper 7. Cartridge Pinouts ************************* General Architecture ************************* SMS contains following main parts: * Zilog Z80 CPU at about 3.3MHz (53.203Mhz/16). * Custom video controller (VDP) based on a well known TMS9918/9928 chip from Texas Instruments, but not equal to it. This chip provides 256x192x16 tiled screen and 64 16-color sprites. The VRAM is separated from main RAM and accessed via VDP ports. * Generic SN76489 PSG made by Texas Instruments. It has 3 tone channels and a noise channel. The clock frequency of this chip appears to be around 4194304Hz. Refer to SN76489 docs for more information. Input/output is implemented via standard Z80 I/O ports, except for the memory mapper registers (see "Memory Mapper"). The Maskable Interrupt (with vector at 0038h) is generated by a VDP chip on each vertical blanking impulse (VBlank). There is also a Non-Maskable Interrupt (with vector at 0066h) which occurs when the user presses the PAUSE button on the SMS console. GameGear has no PAUSE button and uses non-maskable interrupts to acknowledge serial I/O. GG has somewhat upgraded VDP and some changes in the joystick interface and memory mapping, but the rest of its hardware seems to be identical to SMS. Following is a memory map of SMS/GG: -- 10000 ---------------------------------------------- Mirror of RAM at C000-DFFF --- E000 ---------------------------------------------- 8kB of on-board RAM (mirrored at E000-FFFF) --- C000 ---------------------------------------------- 16kB ROM Page #2, Cartridge RAM --- 8000 ---------------------------------------------- 16kB ROM Page #1 --- 4000 ---------------------------------------------- 16kB ROM Page #0 --- 0000 ---------------------------------------------- Locations FFFCh-FFFFh and DFFCh-DFFFh belong to the Memory Mapper (see "Memory Mapper"). ****************************** I/O ports ******************************* Following is an I/O map of SMS/GG: -- DC -- JOYPAD1 ---------------------------------------------- READ-ONLY -- This is one of two joystick ports. Each bit corresponds to a button: 1 for pressed, 0 for released. This port is also mirrored at address C0h (see Pit-Pot cartridge) and probably at some other officially unused addresses. Its bits are laid out as follows: bit MasterSystem GameGear 7 Joypad #2 DOWN Not used 6 Joypad #2 UP Not used 5 Joypad #1 FIRE-B Joypad FIRE-B 4 Joypad #1 FIRE-A Joypad FIRE-A 3 Joypad #1 RIGHT Joypad RIGHT 2 Joypad #1 LEFT Joypad LEFT 1 Joypad #1 DOWN Joypad DOWN 0 Joypad #1 UP Joypad UP -- DD -- JOYPAD2 ---------------------------------- SMS-ONLY -- READ-ONLY -- This is the second of two joystick ports. Each bit corresponds to a button: 1 for pressed, 0 for released. This port is also mirrored at address C1h (see Pit-Pot cartridge) and probably at some other officially unused addresses. Its bits are laid out as bit MasterSystem 7 Lightgun #2 6 Lightgun #1 5 Not used 4 RESET button 3 Joypad #2 FIRE-B 2 Joypad #2 FIRE-A 1 Joypad #2 RIGHT 0 Joypad #2 LEFT This port doesn't appear to be present in GG, as GG has no second joystick and no lightgun. The upper two bits (7 and 6) are also used for automatic nationalization (see "Nationalization"). -- 00 -- JOYPAD3 ----------------------------------- GG-ONLY -- READ-ONLY -- This port is only present in the GG and contains the START button bit and the nationalization bit: bit GameGear 7 START button (1 when pressed, 0 when released) 6 Nationalization (1 in European/American GG, 0 in Japanese GG) -- 7E -- CURLINE/PSGPORT ------------------------------------- READ/WRITE -- This port is performing a dual role. When read, it contains the current scanline number (CURLINE). When written, it serves to output data into the PSG chip (PSGPORT). The 7Eh port also appears to be mirrored at address 7Fh and probably at some other officially unused addresses. -- BE -- VDPDATA --------------------------------------------- READ/WRITE -- This is a VDP chip port used to read and write data from/to VRAM. See "VDP" chapter for more information. -- BF -- VDPSTAT/VDPCTRL ------------------------------------- READ/WRITE -- When read, this port returns the VDP status word as follows: bit Function 7 VBlank Flag, sets to 1 at the beginning of each Vertical Blanking Impulse. This flag resets to 0 after the register is read. 6 5 When written, this port is used to pass VRAM addresses, register numbers, and color numbers to VDP. See "VDP" chapter for more information. The BFh port is also mirrored at address BDh (see SailorMoon cartridge) and probably at some other officially unused addresses. -- 3F -- GUNPORT --------------------------------- SMS-ONLY -- WRITE-ONLY -- This port is only present in the SMS and serves both for lightgun initialization and for determining the system nationalization in SMS. *************************** Nationalization **************************** Both SMS and GG contain circuitry allowing to determine whether the program is running on Japanese or European/American hardware. In SMS, the way to find the hardware nationalization is somewhat tricky. A program is supposed to write ??? In the case of GG, the hardware type can be figured by analyzing the 6th bit of the 00h port. This bit is 1 for European/American GG and 0 for Japanese GG. The GG cartridges also have a data byte which contains information on the ROM size and the market for which cartridge has been manufactured. This byte is located at address 7FFFh (3FFFh in page #1 for mapped cartridges) and its bits have the following meaning: bit Function 7-4 Country Code 0101 Japan 0110 Japan, USA, Europe 0111 USA, Europe 3-0 ROM Size 0000 >128kB 1100 32kB 1101 64kB 1110 128kB ********************************* VDP ********************************** The VDP used in SMS is a heavily modified version of TMS9918/9928 chips made by Texas Instruments and used in such machines as MSX and TI99/4. In the SMS version, all screen modes are gone and replaced by a single tiled mode. Nevertheless, the VDP still has Control and Data ports, as well as Mode Registers and a Status Register. The sprite handling is also changed, and a programmable palette is added for graphics and sprites. The palette contains 32 colors out of 64, 16 for graphics + 16 for sprites. The screen size is 256x192, but may reach 264x192 in the overscan mode. The GG uses the same VDP as SMS, but some CRT-dependent functions (such as overscan) are gone from it, and the palette can be selected from 512 colors instead of 64. The GG screen is actually a 160x144 "window" in the middle of a standard SMS screen. a) VRAM The VideoRAM (VRAM) is a 16kB chunk of memory where VDP stores screen graphics and sprites. The CPU can not access VRAM directly and has to use VDP ports instead. Here is how: Writing to VRAM (address in HL, data written from D) ----------------------------------------------------------------------- LD A,L ; Output lower byte of address into VDPCTRL (port BFh). OUTA (BFh) ; LD A,H ; Output higher byte of address into VDPCTRL. The upper OUTA (BFh) ; two bits must be 00. LD A,C ; Output data into VDPDATA (port BEh). The address will OUTA (BEh) ; be autoincremented after each write. ... ----------------------------------------------------------------------- Reading from VRAM (address in HL, data read into A) ----------------------------------------------------------------------- LD A,L ; Output lower byte of address into VDPCTRL (port BFh). OUTA (BFh) ; LD A,H ; Output higher byte of address into VDPCTRL. The upper OUTA (BFh) ; two bits must be 00. LD A,C ; Input data from VDPDATA (port BEh). The address will INA (BEh) ; be autoincremented after each read. ... ----------------------------------------------------------------------- b) Palette Registers There are 32 palette registers. First 16 of them are used for picture colors, the remaining 16 are used for sprites. As GG offers a bigger selection of colors, its palette registers are 2 bytes each, while SMS registers are 1 byte. Here is how to access the palette: Setting SMS palette (address 00h-1Fh in C, 00BBGGRR value in D) ----------------------------------------------------------------------- LD A,C ; Output the palette address into VDPCTRL (port BFh). OUTA (BFh) LD A,C0h ; Output C0h into VDPCTRL. The upper two bits must OUTA (BFh) ; be 11. LD A,D ; Output values into VDPDATA (port BEh). The register OUTA (BEh) ; number will be autoincremented after each write. ... ----------------------------------------------------------------------- Setting GG palette (address 00h-3Fh in C, 0000BBB0GGG0RRR0 value in DE) ----------------------------------------------------------------------- LD A,C ; Output the palette address into VDPCTRL (port BFh). OUTA (BFh) LD A,C0h ; Output C0h into VDPCTRL. The upper two bits must OUTA (BFh) ; be 11. LD A,E ; Output values into VDPDATA (port BEh), lower byte OUTA (BEh) ; first, upper byte second. The register number will be LD A,D ; autoincremented after each write. OUTA (BEh) ; ... ----------------------------------------------------------------------- c) Mode Registers The VDP has 16 internal registers which control different modes and addresses of graphics and sprites in VRAM. The registers are write-only and accessed as follows: Writing to VDP mode register (register number in C, data in D) ----------------------------------------------------------------------- LD A,D ; Output data into VDPCTRL (port BFh). OUTA (BFh) ; LD A,E ; Output register number ORed with 80h into VDPCTRL. OR A,80h ; The upper four bits must be 10. OUTA (BFh) ; ----------------------------------------------------------------------- -- VDP[0] ------------------------------------------------------------------ General mode register. Its bits are laid out in a following way: bit Function (when bit set to 1) 7 Do not scroll right 2 columns (16 pixels) of the screen. 6 Do not scroll top 2 rows (16 pixels) of the screen. 5 Do not show leftmost column (8 pixels) of the screen. 4 Generate line interrupts (see VDP[???]). 3 Shift all sprites 8 pixels to the left. 2 Unknown 1 Enable overscan (SMS only). Makes screen 264 pixels wide. 0 Unknown -- VDP[1] ------------------------------------------------------------------ General mode register. Its bits are laid out in a following way: bit Function (when bit set to 1) 7 Unused (?) 6 Enable display. No picture is shown when this bit = 0. 5 Generate vertical (VBlank) interrupts. 4 3 2 Unused (?) 1 8x16 sprites. When this bit set to 0, sprites are 8x8. 0 Double all sprite pixels in size (zoomed sprites). **************************** Memory Mapper ***************************** ************************** Cartridge Pinouts *************************** The following data has been provided by