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View topic - Game Gear Rom Paging Chip

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  • Joined: 28 Mar 2011
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Post Posted: Thu May 12, 2011 12:07 am
Well, I received the ICs a few days ago, and will get onto building the circuit as soon as I can make a 'breakout' board for the SMS cartridge slot - still playing around with different ways to get the best results on a double sided board, hope to have it sorted soon though.

TmEE didn't publish a schematic but I did ask him for one, although he hasn't sent it yet (but he did say he'd probably forget and to remind him if he did)


I am interested in the way he seems to use mainly CMOS ICs while yours uses TTL, I thought for an older machine like the SMS it would have to be TTL?


My question about PMs was meant for django (in fact most of that post was, as I was talking about his PCB layout) - but I think it might have been some kind of automatic forum response to the fact that I had used a banned word in that post.
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Post Posted: Thu May 12, 2011 1:35 am
Agent24 wrote
I am interested in the way he seems to use mainly CMOS ICs while yours uses TTL, I thought for an older machine like the SMS it would have to be TTL?


Well, when I draw the circuit it for the first time, I read "somewhere" that 74LS was faster than 74HC. That was the reason. Now that you refer it, I found this application note from Fairchild Semi:

http://www.fairchildsemi.com/an/AN/AN-319.pdf

Ignoring TTL/CMOS logical levels, the 74HC's performance is better than 74LS (conclusion from that document). It is faster and with a lower power consumption. Additionally, Z80's I/O logic levels are TTL:

http://www.nascomhomepage.com/pdf/z80-mostek.pdf (page 79)

but there shouldn't be a problem using 74HC as both GG and SMS are perfect worlds :) Also here in Portugal, 74LS are a little costlier than 74HC...

Kind regards,
CK

PS: the PDFs linked above are extremely oldskool ;) And my technical domain isn't electronics =P
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Post Posted: Thu May 12, 2011 4:17 am
C3R14L.K1L4 wrote

- I assume the address range $0000-$03ff [ROM (unpaged)] does not conflict with the external cartridge's ROM (as viletim confirms above, correct me if I'm wrong).


You have a $0000-$BFFF free for whatever you like. The $03FF thing is the cartridge ROM... it's just a feature of the Sega paging chip. I personally would just leave $0000-$3FFF fixed and call it a day. Most games don't need to swap pages in this area.

C3R14L.K1L4 wrote

- I don't know if the CE pin must be active low (grounded, 0 V) when writing to the FCRs.


The /CE pin on the cartridge slot is the Z80's /MREQ logic OR'd with bit 6 of port $3E. If you read or write to anything in the $0000-$BFFF memory range while you are running code from a cartridge, it will be active (low).


C3R14L.K1L4 wrote

- The cartridge's CE pin controls directly the external PROM's OE pin.



You can do that so long as you somehow ensure that nothing in the cartridge slot conflicts with the ram at $C000-$FFFF.


Also, make sure you keep everything TTL compatible, as the SMS is full of bipolar parts. You can use 74LS but that is obsolete now. 74HCT is a better choice. The Game Gear (and Mega Drive) is CMOS, so not a good comparison.
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Post Posted: Thu May 12, 2011 4:28 am
The ICs I just bought are all 74LS or 74ALS versions, they should be OK, right?
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Post Posted: Thu May 12, 2011 4:33 am
Agent24 wrote
The ICs I just bought are all 74LS or 74ALS versions, they should be OK, right?


Those are fine.
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Post Posted: Thu May 12, 2011 7:31 pm
Last edited by C3R14L.K1L4 on Thu Dec 01, 2011 2:45 pm; edited 1 time in total
Quote
I personally would just leave $0000-$3FFF fixed and call it a day. Most games don't need to swap pages in this area.


Well, I'm just trying to implement a generic mapper, so the 3 FCRs (Frame Controller Registers or whatever you want to call it) are present. That's why I must be sure the machine's internal ROM/BIOS doesn't conflict with the mapping mechanism's first 16 KB block ($0000-$3FFF). Not only for the "probable" :) use of this schematic for playing games (where most doesn't seem to use this first block, as you said) but for software developed by anyone. This is also the main reason why the mapper is done with 7400 ICs and not programmable chips.

Quote
You can do that so long as you somehow ensure that nothing in the cartridge slot conflicts with the ram at $C000-$FFFF.


Guaranteed by U4A's pin 7 (1Y3 which is low when in RAM page, forcing the PROM into "offline" / high-z).

Thanks for the help, viletim.

EDIT: removed incorrect version of the schematic. Check below for a updated version.
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Post Posted: Fri May 13, 2011 7:38 am
C3R14L.K1L4 wrote
. Not only for the "probable" :) use of this schematic for playing games (where most doesn't seem to use this first block, as you said) but for software developed by anyone. This is also the main reason why the mapper is done with 7400 ICs and not programmable chips.


I would recommend the Codemasters or "Korean" mapper for homebrew. They are easier to implement in discrete logic.
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Post Posted: Tue Jun 28, 2011 6:35 am
I know it's been a few weeks but I haven't forgotten about this project ;)

After my first few attempts at making the 'breakout' board to interface to the SMS slot failed badly (bad alignment mostly) I got fed up with it and worked on some other projects for a while.


Anyway, this afternoon with nothing better to do I cobbled together a lightbox\table and started aligning the PCB layers again (doing it on the window is not fun, and the sunlight isn't good in winter anyway) then 'tacked' them in place with an iron before I sent the whole thing through the laminator and this time I think the alignment came out pretty good.

Just need to fix up some areas where I hit it a bit hard with the iron and a couple of tracks spread but otherwise I think I should have a half-decent and finished board by tomorrow.


Then hopefully I can start building the mapper properly...

C3R14L.K1L4: Expect a few questions from me about your circuit when that happens, I'm thinking!
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Post Posted: Tue Jun 28, 2011 10:51 am
OK, I'll await your questions then.
Good luck!
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Post Posted: Thu Jul 28, 2011 1:11 am
Another update - needed more breadboards... have ordered some from eBay... should get here in a couple of weeks
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Post Posted: Mon Aug 22, 2011 4:34 am
Update:

I have the extra breadboards, and I bought more breadboard jumper wire yesterday (taking another look at the schematic I think I will need it!)

Now I've completed the assembly of the PCB which will interface the SMS slot with the breadboard circuitry (see photos). I've used the double-sided PCB and the VIAs are just wire soldered on both sides. Interface cable is solid-core UTP Ethernet cable as this can plug easily into the breadboard directly.

Now, I'll need to assemble the mapper and scavenge some EPROMs for testing...
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Post Posted: Sun Aug 28, 2011 11:18 pm
Got a couple of AT29C256 EEPROMs to test the wiring. Glad I did because they don't work.

Weird thing is the Hang-On Mask ROM from a real Sega cartridge works on the end of my horrible adapter (as long as there's a capacitor right next to it) and yet the AT29C256 won't work in the Hang-On cartridge.

Looks like:
1) Need to fix that first
2) Should probably rethink my adapter - the wires are probably too long for reliable operation. Might add a socket to the adapter, and use that to plug on a soldered protoboard instead. Or maybe a short ribbon cable.

I'll get there eventually though! I hope.... :)
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Post Posted: Mon Aug 29, 2011 5:45 am
If you need decoupling capacitors to make it work, then your power/ground connections are too noisy and have too high resistance/impedance. The twised pair is a poor choice as it may affect signal integrety. Also, your DIY circuit board has a long, short-out-the-bus strip of copper under the edge fingers. What is that for? You could destroy your system if you accidentally remove that thing with the power on (and beleive me, with the SMS2, it's only a matter of time before you do that). I would suggest using a donor cartridge for a finger board next time.
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Post Posted: Mon Aug 29, 2011 6:16 am
Yes I know, the length of the wires are a bit ridiculous, after testing it out and noticing the problems.

However, I had used things of similar length before in other projects without problem, and I thought it would be OK.

I guess I will change it as it's obviously marginal. (Although that still doesn't explain why the AT29C256s don't work even in the official Hang-On cartridge...)

How about a DIL pin header on the board and then I can plug on a short ribbon cable instead, to go to the breadboard? (would be located at front or back of console for minimal length)

I could also create modular protoboard(s) with a DIL socket on them, that could plug straight onto the finger board.


Good point too about the track\strip down the bottom. it was part of the board outline, and was actually going to be filed off when I created the beveled edge on the bottom of the board. I didn't file down enough. I will fix that up too. Even though I have added a power LED to the console, I think you are right, it's only a matter of time before a fatal mistake is made.
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Post Posted: Thu Nov 24, 2011 3:49 am
I've ditched the idea of breadboard completely. Now I'm doing the thing the way I should have in the first place - soldered on protoboard.

I'll be reusing the old double-sided PCB from the previous idea but did as viletim suggested and got rid of that short-out-the-bus strip of copper under the edge fingers.


I started today (enough time wasted already!) but now, I find I have some more questions I need to know before I can proceed.

The mapper here says 4MB (By the way did you mean Megabyte or Megabit there?) and has up to 22 address lines. But can we use ROMs with less capacity\lines than that?

What happens to other address lines which are unused? Just leave them disconnected?


Also, about the different buses : Upperaddress, Z80address and data+control. I assume they are all separate?

eg: a14(9) and a14(37) are NOT connected? and in fact are totally different parts of the circuit?


What about a14(52) through to a21(59) though - they seems to reside all by themselves connected only to U3 - I assume they should actually be connected somewhere else too?
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Post Posted: Thu Nov 24, 2011 5:49 pm
If there are 22 address lines, then that would be 4 megabyte (2^22).
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Post Posted: Thu Nov 24, 2011 7:51 pm
KingMike wrote
If there are 22 address lines, then that would be 4 megabyte (2^22).


Which would mean a 32 Mbit cartridge.

Do those even exist officially?
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Post Posted: Tue Nov 29, 2011 1:23 pm
Sorry for not answering, but I haven't received notifications about replies to this topic.

Yes, 4 MB = 4 Mega Byte. Using JEDEC terms, a capital B means byte ;) (and on the other hand, "b" means bit ^^)

You can leave upper addressing bits unconnected as you wish. Let's say, if you use the lower A0..A15 the mapper will "see" blocks of 64 KB areas, that is, adressing the next 64 KB block (A0...A15 low and A16 high, block starting on FFFFh+1=10000h) it will basically mirror the first 64 KB block.

And of course there are 16 Mb (4MB) or greater PROMs. An example of a 16 Mb (2MB) EEPROM is the IC 29F1610. And there are probably better known ICs..

I'm not sure, but I think there is at least one Game Gear game with a 4 MB ROM..

PS: and the mapper's range can always be expanded by using more mapping registers =) Imagine using 16 8-bit FCRs... 2^(16*8) = 4 GB ;) Overkill for a 3.5 Mhz CPU...........
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Post Posted: Tue Nov 29, 2011 8:58 pm
No worries, yeah I saw you mentioned earlier in this thread you weren't getting emails for it, that's why I sent the PM in case it hadn't got fixed. Maybe if you try un-subscribing and subscribing again? I don't really know though.

Thanks, definitely Megabyte then. I was pretty sure it was that but wanted to check.


Also, can you explain this part? It's the one I have the biggest problem with:

Also, about the different buses : Upperaddress, Z80address and data+control. I assume they are all separate?

eg: a14(9) and a14(37) are NOT connected? and in fact are totally different parts of the circuit?


What about a14(52) through to a21(59) though - they seems to reside all by themselves connected only to U3 - I assume they should actually be connected somewhere else too?
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Post Posted: Tue Nov 29, 2011 9:31 pm
Oh.. My.. God..

sorry, I don't know how I didn't see this. Yes, you're right... U3's outputs 14(52) through to a21(59) connect to the "UpperAdress Bus" exactly like U1 and U2 outputs. They are work exactly like the same (frame control registers).

As for the buses, in a "typical" CPU you always have three buses: Control, Data & Address (Von Neumann architecture).
For (my) convenience I merged C+D in one. For the PROM's address lines, some of them come from the Z80's address lines, bits A0..A13 (because the memory space is divided into 16 KB pages). The other lines (upper address bus) are managed using the FCRs.

You just have to check which lines comes from which bus,. Because of it some come from the Z80 (that is, cartridge) itself and naturally the others from the FCRs.

Just don't forget that *major* error you pointed out. I'll correct it the sooner I can...

Kind regards,
CK
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Post Posted: Wed Nov 30, 2011 7:38 am
First stage and testing complete! (See photos)

Got the boards wired up, tested base functionality with 32k chips. Tried with Hang On ROM and an EPROM copy of Transbot - both worked :)

Next step, I can get onto the extra circuitry, and have fun with 30AWG wire everywhere.



Good to know the issue with U3 is sorted - I had a feeling it should be hooked up the same as U1 and U2 but wanted to check.

C3R14L.K1L4 wrote
You just have to check which lines comes from which bus,. Because of it some come from the Z80 (that is, cartridge) itself and naturally the others from the FCRs.


And the different lines can also be distinguished by the numbers in brackets, correct? (Except for U3's pins which are wrong)

eg:all data lines are connected to the same thing, for example:
d0(1) wire will physically connect to cartridge slot, to U1-U3 and the EEPROM as well?

While a14(9) and a14(37) NEVER connect to each other (totally separate parts of the circuit)?

Just want to make this all clear to myself, so I don't have any doubts. I'm pretty sure I understand it but would hate to wire it all up only to have to pull it apart again ^^
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Post Posted: Thu Dec 01, 2011 1:54 pm
Last edited by C3R14L.K1L4 on Thu Dec 01, 2011 6:41 pm; edited 1 time in total
Quote
First stage and testing complete! (See photos)

Got the boards wired up, tested base functionality with 32k chips. Tried with Hang On ROM and an EPROM copy of Transbot - both worked :)

Next step, I can get onto the extra circuitry, and have fun with 30AWG wire everywhere.


You're on the good track! I hope you have fun, then ;)

Quote
And the different lines can also be distinguished by the numbers in brackets, correct? (Except for U3's pins which are wrong)


Yes. Those numbers are the IDs of the virtual wires on the netlist (how the simulator stores the circuit). But try not to confuse the numbers..

Quote
d0(1) wire will physically connect to cartridge slot, to U1-U3 and the EEPROM as well?


Naturally, the data lines must be connected to the cartridge, the FCRs and the "ROM". For instance, if the CPU writes a value to a FCR, the data lines carry that information to physical FCR. When the CPU wants to read a specific address from the ROM, the data lines carry the result from the ROM into the CPU.

Quote
Just want to make this all clear to myself, so I don't have any doubts. I'm pretty sure I understand it but would hate to wire it all up only to have to pull it apart again ^^


Exactly. This is not a war, so you can ask questions "before" ;)
Good work!

CK.
sms - gg 4 MB memory mapper.ms1.pdf.zip (23.22 KB)
latest version of the mapper
sms - gg 4 MB memory mapper.zip (182.67 KB)
multisim 11 file

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Multisim 11 diesign File
Post Posted: Thu Dec 01, 2011 4:35 pm
Hi C3R14L.K1L4,

Can you post the latest Multisim 11 schematic as well?

I'm messing around with this on my off time.........when I have it. My College Exams are happening over the next couple of weeks so, it probably won't be until after the new year before I'll have time to actually even attempt anything.

Regardless, I want to try interfacing an 8MBit Flash chip to start and see if I can get that running at least. I'll be going with the CPLD approach.

I'm anxious to see how you guys make out with the 7400 series circuit. :)

Fun Stuff.

-Gerry
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Post Posted: Thu Dec 01, 2011 6:45 pm
Gerry_MAN wrote
Can you post the latest Multisim 11 schematic as well?

Check the above post, m8 :)

Gerry_MAN wrote
I'm anxious to see how you guys make out with the 7400 series circuit. :)

Agent24 is the operative here, he's the one with the cables ;)

Good luck with the exams!

Kind regards,
CK.
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Post Posted: Fri Dec 02, 2011 9:20 am
More work done: added more than half the ICs and done about 1/3 the wiring for them.

Bonus question: Why do the a14 and a15 lines from the SMS not go directly to the ROM, rather through the other circuitry instead?
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Post Posted: Fri Dec 02, 2011 4:57 pm
Agent24 wrote
More work done: added more than half the ICs and done about 1/3 the wiring for them.

Bonus question: Why do the a14 and a15 lines from the SMS not go directly to the ROM, rather through the other circuitry instead?


Very Nice! I love the wiring job. Looks like fun!!
Keep us posted. :)

-Gerry
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A14 & A15 Address Lines - Used by Mapper for Memory Bank Switching
Post Posted: Fri Dec 02, 2011 5:30 pm
Agent24 wrote
More work done: added more than half the ICs and done about 1/3 the wiring for them.

Bonus question: Why do the a14 and a15 lines from the SMS not go directly to the ROM, rather through the other circuitry instead?


I'm pretty sure that A14 and A15 lines are used for switching the divided ROM Memory Banks, which determines which bank is selected and routed to the Z80.

The A14 & A15 are the two highest Significant Bits on the Z80 address bus. So they are used for switching when you are using a mapper.
If your memory is large enough to fill up and spill over to the point where it would need to use the A14 & A15 addresses;
as soon as this happens and the A14 changes to a Logic HIGH, that signal is instead used by the mapper circuit to switch to an alternate Memory Slot.
This concept applies to both A14 & 15 lines.

Using these lines together you essentially have a 2-Bit control bus if you will. This provides 4 possible logic combinations, 00 01 10 11.
In turn the mapper uses these signals to switch between 4 separate ROM Memory Banks and then routes the Data in those locations to the Z80.

That's sort of my understanding on it anyhow.
Although there might be more involved than what I've stated.

-Gerry
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Post Posted: Fri Dec 02, 2011 6:51 pm
Gerry_MAN wrote
Agent24 wrote
More work done: added more than half the ICs and done about 1/3 the wiring for them.

Bonus question: Why do the a14 and a15 lines from the SMS not go directly to the ROM, rather through the other circuitry instead?


I'm pretty sure that A14 and A15 lines are used for switching the divided ROM Memory Banks, which determines which bank is selected and routed to the Z80.


Seems Gerry beat me up to it ;)
Exactly.

If you check the schematic, the A14 & A15 lines have a label "16 KB decoding". The mapper uses these lines and the FCRs to swap the PROMs contents into a given block. For more details check this link (sega mapper):
http://www.smspower.org/Development/Mappers

Kind regards,
CK.

BTW Agent, it's getting pretty! Keep the good work ;)
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Post Posted: Sat Dec 03, 2011 11:51 am
Back again, I have good news and bad news..

Good news is, I finished the circuit, and nothing caught fire during testing ;)

Bad news (I think you can guess) that it doesn't seem to work. But it's odd - it does *nothing* - the SMS boots straight to Alex Kidd and that's it.

No lockup, no "Software Error" message. It seems that it is doing nothing at all.


I tried with a W29C020 2Mbit EEPROM I had to hand, 2 different 256k games (Sonic 1 and Super Space Invaders) but neither worked.

I will re-check the wiring probably tomorrow and see if I missed anything obvious (although I made sure to triple-check everything as I built it)


Only changes from your design were that I only connected the address lines up to A17 (the 2Mbit chip only goes up that far) and I added +5v connection to /WR pin of the EEPROM (I think this is necessary for proper operation in any case)


It could even be a problem with the EEPROM, it was pulled from an old motherboard so perhaps is unsuitable for this application (presence of bootblock etc)?

The programmer software also had an option about sector size, default was 128 but not sure if I should have changed this.


Will try to find out, find some other EEPROMs to test, preferably ones not from a motherboard, probably I did something wrong here!
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Post Posted: Sat Dec 03, 2011 12:05 pm
You only get SOFTWARE ERROR if the TMR SEGA is found but the checksum or region is wrong.
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Post Posted: Sat Dec 03, 2011 2:30 pm
Quote
Good news is, I finished the circuit, and nothing caught fire during testing ;)


Ooh... ;)

Quote
Bad news (I think you can guess) that it doesn't seem to work. But it's odd - it does *nothing* - the SMS boots straight to Alex Kidd and that's it.


That's because the SMS detected nothing on the cartridge and it boots from the internal ROM. However, I don't remember the details of how this is done (I knew in the past), so I'll have to investigate.

Quote
Only changes from your design were that I only connected the address lines up to A17 (the 2Mbit chip only goes up that far)


That's OK. It's to be used like that.

Quote
and I added +5v connection to /WR pin of the EEPROM (I think this is necessary for proper operation in any case)


And you should.
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Post Posted: Sun Dec 04, 2011 4:17 am
C3R14L.K1L4 wrote
Quote
Bad news (I think you can guess) that it doesn't seem to work. But it's odd - it does *nothing* - the SMS boots straight to Alex Kidd and that's it.


That's because the SMS detected nothing on the cartridge and it boots from the internal ROM. However, I don't remember the details of how this is done (I knew in the past), so I'll have to investigate.


Unfortunately I never knew, so I can't really proceed any further at the moment.

I guess in the meantime I should start reading the documentation about the SMS on this site and about digital circuits in general and hopefully then I can do something more useful here.

Perhaps the study of the designs some others did in CPLDs will provide more information?
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RE:Game Gear Rom Paging Chip
Post Posted: Sun Dec 04, 2011 5:44 am
Hey Guys,

I also entered this schematic into an Altera EPM7128SLC84 CPLD and I wired it to my SMS2 cartridge in place of the 315-5912 mapper IC.
When I tried to run it on the SMS2 console with the 8-MBit version of "Virtua fighter Animation" for the SMS, I got the same results.....Just a blank screen.

Although I did change a couple of things on the schematic, but not anything critical that would affect the loading to my knowledge.

I'm trying a few different things to test, but no successful results as of yet.

I've attached my Quartus Schematic and the Pin assignment map.

-Gerry
CPLD_TEST_003b.jpg (146.17 KB)
CPLD_TEST_003b.jpg
Pin_assignments2.jpg (137.04 KB)
Pin_assignments2.jpg

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Post Posted: Sun Dec 04, 2011 7:40 am
Gerry_MAN wrote
I also entered this schematic into an Altera EPM7128SLC84 CPLD and I wired it to my SMS2 cartridge in place of the 315-5912 mapper IC.
When I tried to run it on the SMS2 console with the 8-MBit version of "Virtua fighter Animation" for the SMS, I got the same results.....Just a blank screen.


Something must be different with your implementation because that is not the same as the result I got.

My SMS seems to ignore the circuit and booted to Alex Kidd instead.
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Post Posted: Sun Dec 04, 2011 8:21 am
Yeah, my SMS2 console is the one with Sonic 1 installed in system.

It didn't boot into that at all. Just a black screen. :(

However, I've got my CPLD interfaced off of a UP1 Development board, and have the UP1 board and Console sharing the GND lines.
They are running off their own separate DC Power supplies, so I think I should rig up a CPLD socket directly to the Board I'm using for the interface.
That way they will all be running off the same power source. That could be causing an issue.

Although I've done several other CPLD interfacing projects similar to this, while interfacing to other computer systems in the same manner,
and they worked fine. So it's kind of a toss up as to what the heart of the issue is.

But I figure I'll try changing this regardless.

-Gerry
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Post Posted: Sun Dec 04, 2011 11:57 am
Here below is viletim's schematic design that I'm testing on the CPLD also. The fact that I'm using a larger CPLD....the Altera 128 Macrocell, I added the external 8-input NAND gate into the CPLD schematic as I had the room.

I actually just removed the Inverter gate that it connected to and made it an 8-input AND gate. Essentially the same thing right. Perhaps this was a simple fix to accommodate the parts that he had at his disposal at the time when building the prototype board?

Anyhow, I'm thinking to that I should check my Flash chip same as you did Agent24. If the ROM image didn't load onto the Flash chip properly, all this would be redundant.

I'll do that first thing when I get the time.

-Gerry
CPLD_TEST_004.jpg (340.98 KB)
CPLD_TEST_004.jpg
Pin_assignments3.jpg (87.83 KB)
Pin_assignments3.jpg

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Post Posted: Sun Dec 04, 2011 4:22 pm
I've searched trough the WIKI and some very old documents I have and found nothing about how do the SMS (or the GG) detect a cartridge in the slot. I wouldn't be surprised if it was something as simple as some of the GND lines to be just grounded...
I say this because sometimes I insert a game in the cartridge slot and my SMS boots from its built-in game (Alex Kidd). To correct it I just have to reinsert the game until it works =P
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Post Posted: Sun Dec 04, 2011 8:12 pm
Export systems detect games by checking for the TMR SEGA string in the header. Japanese systems check for non-repeated values in the middle 4 bits in the first 256 bytes.

http://www.smspower.org/Development/BIOSes
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Post Posted: Sun Dec 04, 2011 8:17 pm
Well, I've verified that my Flash chip works. The Virtua Fighter Animation SMS ROM does in fact load when I use the 315-5912 Sega Mapper, so at least that is out of the way and I've confirmed that it does work.

Looking at viletim's schematic the INHIBIT line, I'm wondering what contact on the SMS I connect that to, currently I've just tied that to GND ??

I've got nRESET connected to /RESET on the SMS cart edge and I have nCEout connecting to my flash chips /OE line. I've also notices that the /RD line is not used in this circuit.

When I get the time after my exams I'll etch a PCB that has a PLCC socket for the Altera chip. I'm thinking my wires may be causing some interference resulting in cross-talk on the various ADD/DATA/CNTRL Buses.

For now though I'll have to put this on the back burner, Exams are my priority for the next week and a bit. But I may pick away at when I need a break.

I'll keep you guys posted.

-Gerry
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Post Posted: Sun Dec 04, 2011 8:17 pm
Last edited by Gerry_MAN on Sun Dec 04, 2011 8:48 pm; edited 1 time in total
My post Repeated for some reason. Sorry guys.

-Gerry
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Post Posted: Sun Dec 04, 2011 8:42 pm
Maxim wrote
Export systems detect games by checking for the TMR SEGA string in the header. Japanese systems check for non-repeated values in the middle 4 bits in the first 256 bytes.

http://www.smspower.org/Development/BIOSes

Maxim, so how do you explain that strange "phenomena" that sometimes happens when I insert a cartridge into SMS (loads the built-in game and not the cartridge's ROM)? I can only think of stuff like the ext. ROM not getting voltage from the power supply (contact problems for instance with GND or VCC pins...)

So in Agent24's case, the SMS is not detecting the header on his ROM, correct?

BTW, good luck with your exams, Gerry_MAN. Of course, it should be your main concern now ;)
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Post Posted: Sun Dec 04, 2011 9:06 pm
Thanks for the good luck...... I'll need it. :(

Before I head out, can you guys comment anything regarding the current connections I'm using with viletim's schematic?

From my Previous post.......:

The INHIBIT input line which I have designated as PIN_55 for the CPLD (all the CPLD pins are highlighted in yellow on my image link below).
I'm wondering what contact on the SMS I connect this to? currently I've just tied that to GND ??

I've also got nRESET connected to /RESET on the SMS cart edge and I have nCEout connecting to my flash chips /OE line.
I currently do not have a RAM chip interfaced so the output "nSRAM" I've just left it unconnected. I've also noticed that the /RD line is not used in this circuit. Think that is an issue?

http://www.smspower.org/forums/files/cpld_test_004_886.jpg

http://www.smspower.org/forums/files/pin_assignments3_200.jpg

Any comments??

-Gerry
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Post Posted: Sun Dec 04, 2011 9:10 pm
I just looked at the schematic again and just saw the NOT gate connected to the Tristate buffers. I'm guessing tying the INHIBIT line to GND is Bad. :(

http://sub.allaboutcircuits.com/images/04152.png

-Gerry
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Post Posted: Sun Dec 04, 2011 9:25 pm
Quote
I've also got nRESET connected to /RESET on the SMS cart edge and I have nCEout connecting to my flash chips /OE line.
I currently do not have a RAM chip interfaced so the output "nSRAM" I've just left it unconnected. I've also noticed that the /RD line is not used in this circuit. Think that is an issue?


Probably it is. As I want to prevent conflicts with the mapping scheme, I have necessarily logic for it. In my mapper, the PROM's /CE is a NAND (U7B) of the Read bit, connector's CE (or CrtOe..) and a line specifying if the Z80 is accessing the RAM's area (from U4A's 1Y3 output). In sum, the PROM's output is activated when the Z80 wants to read data from the cartridge except in the RAM's address range (last 16 KB page).

Quote
The INHIBIT input line which I have designated as PIN_55 for the CPLD (all the CPLD pins are highlighted in yellow on my image link below).
I'm wondering what contact on the SMS I connect this to? currently I've just tied that to GND ??


I don't know Viletim's scheme, as I built mine from scratch from the documentation available on this site. What is that "INHIBIT" line for?

Edit: From what I've analyzed, the inhibit bit seems to disable the PROM's addressing, I think. In my mapper the same is achieved trough the use of FCR's output control (OC) which is a function of the region where the CPU is (U4A, page decoding) and also U7B as explained above.
I bet this logic can be simplified, but I don't grasp the SMS's inner workings in order to achieve this.
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Post Posted: Sun Dec 04, 2011 9:37 pm
Gerry_MAN wrote
Thanks for the good luck...... I'll need it. :(

Before I head out, can you guys comment anything regarding the current connections I'm using with viletim's schematic?


Have you looked at these links?

http://www.smspower.org/forums/viewtopic.php?t=13203

http://etim.net.au/temp/maxplus10.2/


C3R14L.K1L4 wrote
I've searched trough the WIKI and some very old documents I have and found nothing about how do the SMS (or the GG) detect a cartridge in the slot. I wouldn't be surprised if it was something as simple as some of the GND lines to be just grounded...
I say this because sometimes I insert a game in the cartridge slot and my SMS boots from its built-in game (Alex Kidd). To correct it I just have to reinsert the game until it works =P


C3R14L.K1L4 wrote
how do you explain that strange "phenomena" that sometimes happens when I insert a cartridge into SMS (loads the built-in game and not the cartridge's ROM)? I can only think of stuff like the ext. ROM not getting voltage from the power supply (contact problems for instance with GND or VCC pins...)


I am pretty sure in those cases it is dirty contacts on the cartridge board.

A friend of mine brought some retail games over a week ago and none of them would load first time. I opened each one, cleaned the contacts on the board and then they worked perfectly.

The repeated inserting\removal of the cartridge will clean the contacts as well from the SMS slot connector basically scraping dirt off every time you do so.


As I understand with the EEPROMs, you give them +5v, then pull /CE and /OE low, /WR high, and then send the appropriate data to it on the address lines for the address in the EEPROM you wish to read.

The EEPROM then sends you back the data for that address through the data lines and you do whatever with it that you want to do.

(This is what the datasheets usually say, anyway!)


I guess this is basically what the SMS does, and then it waits to see if it gets any sensible output from the cartridge? This is the bit I suppose we are stuck on.


Then as Maxim said, If it doesn't get the "TMR SEGA" (or the Japan equivalent) then it ignores the whole thing (I guess!) if it gets TMR SEGA but a bad checksum\region it writes "Software error" and stops, or if everything works out it loads the game.

And if the EEPROM in the cartridge and the internal BIOS both try to output their data at once (or any other strange thing happens) the system hangs.
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Post Posted: Sun Dec 04, 2011 9:45 pm
Last edited by Maxim on Sun Dec 04, 2011 9:46 pm; edited 1 time in total
Bad connections on the address and data lines will most likely block the TMR SEGA from being read correctly. The ideal way (!) to test the cartridge is probably to put it in a known-good SMSReader and dump it as that can give clues as to the problem.
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Post Posted: Sun Dec 04, 2011 9:46 pm
@ Agent24,

Yeah I have looked at those links several times and used allot of the info to try and help.
So thanks for that regardless. :)

I guess some brainstorming is in order.

-Gerry
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Post Posted: Sun Dec 04, 2011 10:02 pm
Maxim wrote
Bad connections on the address and data lines will most likely block the TMR SEGA from being read correctly. The ideal way (!) to test the cartridge is probably to put it in a known-good SMSReader and dump it as that can give clues as to the problem.


Now that sounds like a pretty useful idea, why did I not think of that ;)
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Post Posted: Mon Dec 05, 2011 5:34 am
Well, this INHIBIT line eludes me....:(

I've tried tying it to Vcc and GND and still no go. But there could be more issues preventing it from loading.
It's actually started to give a high pitched buzzing sound and a black screen since switching to a PLCC socket.

See Pictures:
This image was before I added a noise filter cap to the CPLD Vcc & GND. There is one in place now so I know that is not an issue.
However etching a board with this will be way more stable and I'll add a JTAG port so I won't have to remove the CPLD for re-programing.

Anyhow, still not functioning.
I'll have to pick away at it yet again.

-Gerry
SMS_8MBIT_CPLD_001.jpg (169.18 KB)
SMS_8MBIT_CPLD_001.jpg
SMS_8MBIT_CPLD_003.jpg (118.71 KB)
SMS_8MBIT_CPLD_003.jpg
SMS_8MBIT_CPLD_004.jpg (125.27 KB)
SMS_8MBIT_CPLD_004.jpg

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Post Posted: Mon Dec 05, 2011 9:11 am
Gerry_MAN wrote
Well, this INHIBIT line eludes me....:(


The word 'inhibit' is the inverse of 'enable' in electronics. The INHIBIT line is an active high input which can be used to inhibit the operation of chip. When active, the A14in and A15in signals directed to A14out and A15out, and A16out-A19out are put into a high impedance mode. I don't remember why I included this feature. It was probably useful to me at the time but you should just connect this input to ground.

Gerry_MAN wrote
I've also got nRESET connected to /RESET on the SMS cart edge and I have nCEout connecting to my flash chips /OE line.
I currently do not have a RAM chip interfaced so the output "nSRAM" I've just left it unconnected. I've also noticed that the /RD line is not used in this circuit. Think that is an issue?


The reset signal is required. It might be worth double checking that your SMS hardware actually connects the /RESET pin. My SMS1 and SMS2 does buy my converter for the Mega Drive does not. Connecting nCEout to /OE, and leaving nSRAM unconnected is fine. The /RD is not used because there is nothing to read. You write the page number to the mapper and it maps it for you. You can't read any data out of the mapper - it's write only.

I advise you to start with a 32k game and work your way up from there. I have never tested my design with anything larger than 4Mbit, though it supports up to 8Mbit in theory, you should use something smaller for initial testing.

From your photo I can see the wires you are using for power and ground are too thin. These old CPLDs require a lot of power, thin wires will cause a voltage drop during current spikes.
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