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  • Joined: 09 Jan 2008
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Game Gear Rom Paging Chip
Post Posted: Thu Jan 10, 2008 6:54 am
Hello everyone,

I've been collecting Game Gear stuff for quite a few years now, I've been considering making a rewritable cartridge for the game gear.

I have a few questions....

Does a GG cart use a paging chip, I've pulled apart a few and
have yet to see one.

I've noticed that the hacked SMS carts on the net use an eprom.
What would be stopping me from using an eeprom.

Thanks Dave
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Post Posted: Thu Jan 10, 2008 7:45 am
Most carts have a combined mapper and ROM chip, especially on the GG where there's less room in the cart. If you substitute an EPROM you can get up to 48KB (but I think 32KB is easier).

You can try taking a mapper chip from a Master System game but I think you'll have a hard time fitting it into the cart.
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Post Posted: Thu Jan 10, 2008 11:20 am
My SMS/GG mapper idea requires 6 chips and it would not have been fully compatible. And it needs little more work... I think you can get something nice with programmable logic.
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Post Posted: Tue Jan 29, 2008 6:47 pm
Last edited by C3R14L.K1L4 on Thu Dec 01, 2011 2:48 pm; edited 1 time in total
hi,

in both GG and SMS, when the cpu is accessing the first 1 KB internal ROM (aka bios) does the machine's internal circuit disable external ROM (ie rom bus) or must the mapper prevent this?
ie, resuming, if cartridge bus shows activity in the so called bios must the mapper disable the external rom data signals?

other question, does the "bios" load the FCR with the correct values or must the mapper do this upon it's "power-up" ?

kind regards,
CK

EDIT: latest version of the mapper here:
http://www.smspower.org/forums/viewtopic.php?p=69122#69122

Please warn me if this link gets out of date.
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Post Posted: Tue Jan 29, 2008 7:37 pm
I think the console disables the cart in that region when the BIOS is enabled, else 32KB mapperless games wouldn't boot. Mappers should default page 0 and 99% of games will have code at startup to initialise the mapper.
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Post Posted: Tue Jan 29, 2008 8:45 pm
Nice point. Thanks.

That way my circuit gets much simpler. Perhaps before the end of this week I'll post it here.
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Post Posted: Wed Jan 30, 2008 9:42 am
Oh, and:
00000000: F3            DI                      ; Disable interrupts
00000001: 21 00 00      LD HL,0000h             ; Set paging registers
00000004: 22 FC FF      LD (FFFCh),HL           ; -> Disable SRAM
00000007: 21 01 02      LD HL,0201h             ; -> 0:0, 1:1, 2:2
0000000A: 22 FE FF      LD (FFFEh),HL   

The first 12 bytes of the GG BIOS. BIOSless systems will depend on the mapper to initialise itself properly.
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Post Posted: Wed Jan 30, 2008 2:32 pm
Yeah, I've checked with meka's debugger some GG behaviour as well as SMS and both have in the startup the FCRs loaded with 00h. When the CPU 'arrives' at the rom code the FCRs have changed to 0-1-2.
It's just because to force the mapper circuit to preload those values at startup forces me to add some logic wich I hope would be unnecessary... :P
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Post Posted: Wed Jan 30, 2008 3:50 pm
Meka initialises the mapper registers because it is not being 100% accurate. On a real system you will get one of:

- No mapper, 32KB ROM mapped to 0-$7fff, no intialisation necessary
- Mapper, initialises itself to some known state at boot thanks to /RESET on cart slot, probably slots set to 0/1/2
- Mapper, fixes first 1KB, code in that region initialises mapper
- Mapper, slot 0 (and maybe 1) unmappable, fixed to start of ROM, code in that region initialises mapper for higher regions before accessing
- System has a BIOS that initialises the mapper before reading anything

In an emulator, a simplifying case is to ignore the BIOS, initialise the system to a typical post-BIOS state (for games that rely on it) and treat mapperless games as if they have mappers*.

* If a 32KB game accessed the mapper it would be an interesting way to make it "emulator-incompatible".
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Post Posted: Thu Jan 31, 2008 12:58 am
Last edited by C3R14L.K1L4 on Tue Apr 19, 2011 4:51 pm; edited 5 times in total
here it is in it's very early 'alpha' stage :P

I think it has all the logic required for maping the FCRs and corresponding pages. Uses 8 bit FCRs so it can map up to 16 KB x (2^8) bytes = 4 MB.
However it hasn't the capability to load predefined values on the FCRs upon startup.

I was hoping if anyone could build or debug the circuit for me, so that, if needed, I could apply the required "patches" ;)

EDIT: the attached schematic is "incorrect". I've removed it, so check below for a recent version.
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Post Posted: Thu Jan 31, 2008 4:13 am
Semi-unrelated but any suggestions for a decent freeware circuit design tool?
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Post Posted: Thu Jan 31, 2008 6:37 am
I like this method !!!
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Post Posted: Thu Jan 31, 2008 6:54 pm
djbass wrote
Semi-unrelated but any suggestions for a decent freeware circuit design tool?
I use PSPICE.
I don't know if it's freeware btw *cough*
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Post Posted: Fri Feb 01, 2008 2:03 am
For debugging and prototyping I normaly use bread boards:



If I only knew how to build pcbs...
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Post Posted: Sun Feb 03, 2008 11:03 pm
It´s a pain to do a pcb the first time,
it doesn´t matter which method you use,
you will need a lot of time, tools, material.

I think the fastest and cheapest way to get a good pcb
is to let it make from someone who has the
knowledge to to this and lives in your country.

search for a portuguese hobbyist electronic forum
and ask for someone who will do it for you.
I´m sure there are many people who want to do this.

even if you have to pay 20 euro it is much cheaper
if you do it yourself. And you get usable quality
without trying it over and over again.
Better use the time for more development.


If you can wait 3 weeks or 4 i can ask a friend
who can make you one and sent it to you at no cost.
(master system Version)

But I think I first build it on my own and
let you know if it works.

have a look at the attachment

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Post Posted: Sun Feb 03, 2008 11:09 pm
Is there no /CE on the gamegear?
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Post Posted: Mon Feb 04, 2008 1:56 am
django wrote
Is there no /CE on the gamegear?


Oops, my fault. Didn't notice that...
But now I have a problem. "Chip Enable" is active low when? When the machine is accessing the external ROM, 0100h-BFFFh?

About the pcb stuff, well I should seek someone to help me build it, but not while the circuit is still 'unchecked'...

And your pcb is 5*! The smiley is your watermark? ;)
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Post Posted: Mon Feb 04, 2008 8:40 am
C3R14L.K1L4 wrote
django wrote
Is there no /CE on the gamegear?


Oops, my fault. Didn't notice that...
But now I have a problem. "Chip Enable" is active low when? When the machine is accessing the external ROM, 0100h-BFFFh?


On the Master System /CE is active for the entire range ($0000-$FFFF) and you do the address decoding yourself. I suppose the Game Gear is the same...
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Post Posted: Mon Feb 04, 2008 2:32 pm
So, it's not needed, right? Or has a function similar to MREQ? When the cpu wants to access some address, both go low... ?
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Post Posted: Mon Feb 04, 2008 3:03 pm
/CE is /MREQ or'd with the cartridge slot enable bit. You should use it instead of /MREQ else you may end up conflicting with the internal rom (or card slot on the SMS).
 
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Post Posted: Tue Feb 05, 2008 4:15 am
Humm, thanks. By the way, how do you know that? ;)
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Post Posted: Tue Feb 05, 2008 12:47 pm
C3R14L.K1L4 wrote
Humm, thanks. By the way, how do you know that? ;)


There are lots of /CE lines - one for cart slot, explasion slot, internal rom, etc. Each is just /MREQ gated with the relevent bit of port $3E. I don't remember where I learned this, but it was probably from somebody's forum post or maybe it's in the docs somewhere.
 
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Post Posted: Tue Feb 12, 2008 2:09 am
Last edited by C3R14L.K1L4 on Tue Apr 19, 2011 4:49 pm; edited 1 time in total
Sorry for the delay. Here it is, as a pdf.

And, could the topic's name be changed to "GG/SMS Rom paging circuitry?" because it also applies to the sms.

EDIT: PDF removed. Latest version below.
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Post Posted: Sun Aug 31, 2008 9:58 am
Hello everyone,

has the 4mb mempry mapper been made yet from the schematic
and confirmed working?

which eeprom's can be used with the circuit?

thanks Dave
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Custom SMS / GG Mapper
Post Posted: Sat Mar 05, 2011 6:01 am
Hey guys,

I realize this is a long abandoned topic, but did anything ever come of this?

I can't believe I never saw or read about this topic throughout all the research I did for my GG flash cart. I just noticed a reference to it on Snow_Cat's SEGA Eagle Library file.

You guys think this Mapper schematic is sound? I could try building it if you think it might work.

And also.... I guess the SMS Sonic Blast cartridge is now a possible DIY flash cart. I didn't know about this SMS cartridge using the 315-5912 mapper until a few moments ago. Crazy!


Anyhow,
any comments regarding this abandoned Custom Mapper schematic?.......anyone?

Regards,
-Gerry
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Post Posted: Mon Mar 07, 2011 5:35 pm
oliverthepig wrote
has the 4mb mempry mapper been made yet from the schematic and confirmed working?

As far as I know, nope.

oliverthepig wrote
which eeprom's can be used with the circuit?

Any "programmable chip" which has the required signals :) The 8 data bits, a decent amount of address bits (maximum 22 lines = 4 MB) and the usual output enable control line.

Gerry_MAN wrote
I realize this is a long abandoned topic, but did anything ever come of this?

Yes it is (abandoned). I never got the time nor the resources to continue with this. I just tried to build the base stuff for anyone to continue. I will try to help with anything my mind can.

Gerry_MAN wrote
You guys think this Mapper schematic is sound? I could try building it if you think it might work.

I simulated it in all my possibilities (lots of truth tables) but I didn't have the resources nor the... cough, cough.. patience to build it. All my time was needed for the University. Consequently, I can't tell you it will work. I fully recommend testing it using a CPLD or a FPGA, so you don't have a mess there (I have no experience with those devices).

Kind regards,
CK
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Custom Mapper
Post Posted: Mon Mar 07, 2011 9:02 pm
Wow Ok,

That's really amazing.

I think I'll take a stab at it, once I can mange the time. I'm in the same situation as you were in..... School is dominating the schedule. :(

So maybe after this semester is over........hopefully.

Cheers!,
-Gerry
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Post Posted: Tue Mar 08, 2011 12:47 am
Good luck, then!

If you need anything, don't be afraid to ask.

Kind regards,
CK
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Post Posted: Sat Apr 02, 2011 1:09 am
I am also quite interested in building an SMS cartridge with mapper that uses standard ICs.

I liked the look of the Everdrive until I saw the price...

But with a handful of these ICs it will be much cheaper, also I can make my own PCBs very easily so that is no problem.

If I can help in any way to get this project idea running I will be happy to!


Ps: How easy are CPLD \ FPGAs to use? I have a couple of Altera or Xilinx (can't remember which) devices someone gave me, not sure if they are any good but might be interesting to try out.
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Post Posted: Sat Apr 02, 2011 1:53 am
Hi Agent24,

The CPLD's are pretty straight forward but will require getting familiar with the appropriate implementation software before you can get anywhere.

The Altera series CPLDs use the Altera Quartus II software for programming the chips. Available on their website for download.
With the software you can use either a Block diagram format of programming, which is essentially a digital schematic layout using standard digital components or gates.
Or you can use the VHDL code format. I use the Block Diagram layout which is essentially a digital Schematic and the Quartus software compiles that schematic layout
accordingly, to the chip and connects the chips pins to that design as you lay out in a "PIN PLANER" menu within the software.

So essentially the CPLD will replace a large digital circuit of up to say 5000 Gates, but this also depends on the chips you use. Some CPLD's have many gates
and some have very few.The Xilinx is essentially the same but uses a different software. I have yet to try the Xilinx family of chips.

You will also need to purchase a $10 "USB-Blaster" programming adapter in order to program them. Most CPLD's have 10 Pins on the chip that are reserved for a form
of serial programming. This has become a standard and is called JTAG or also called "ISP" which stands for "In Service Programming". This standard allows the chips
to be programmed once the chips are already assembled onto their PCB. Hence the name. Most Dev boards use this JTAG format for interfacing the boards to a PC.

Some more details & Pictures here on my website: http://www.digital-circuitry.com/MyLAB_CPLD_PROG.htm I would just go to the Altera website and do a little research. It's pretty awesome! www.altera.com

Also check out this link here http://en.wikipedia.org/wiki/Joint_Test_Action_Group

Hope this helps a bit.
Regards,
-Gerry

P.S.
If you can try to build the Mapper Circuit and get it working that would be sweet!! I'm so busy with school I just haven't had the time to try this yet.
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Post Posted: Sat Apr 02, 2011 2:18 am
Thanks for the speedy reply with info on the ICs!

Turns out I've got an Xilinx XC9536 and an Altera EPM7032 - again not sure if they have enough pins etc for doing this but I guess we can find out... Ps: had a look at the download for the Xilinx software - Full install for ISE Design Suite is 4GB! Might take a while to download...

The person I got them from has made his own breakout boards but failed to protect them properly so the tracks are quite badly corroded, guess I will have to fix that problem first.

I know a little about JTAG already, have used it once to recover firmware on a bricked ADSL router. At that time I just used a basic design with resistors, as suggested on the OpenWRT wiki.

I could probably make a better JTAG programmer though - in fact a USB version might be just the thing to practice my SMD soldering skills on... ;)



As for the 74 series mapper, I could certainly build it but probably have next to no idea how to fix it if it didn't work.

I can easily make a PCB from schematic (have done it many times) but the actual circuit design itself eludes me :(

I understand the function of AND\NAND and such gates, but don't really understand how these translate into shuffling around memory addresses for a CPU!

Do you know of any resources where I can study and hopefully learn more about this? I know it must be a very wide and in-depth topic but there has to be something.
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Post Posted: Sat Apr 02, 2011 3:17 am
Hi Agent24,

I would suggest checking out http://www.allaboutcircuits.com/

They have free 500 page textbooks for download and cover from the very basics in both Analog & Digital electronics
to the more advanced level stuff. It's a great resource and I use it all the time.

-Gerry
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Post Posted: Sun Apr 03, 2011 9:31 pm
Thanks for those links. Looks like I will be doing a fair bit of reading!

Looks like the idea of building a USB JTAG for these things is a bad idea (proprietary design for the official programmer, too expensive to reproduce properly I think)

But it seems you can also program officially through the parallel port, which should work just fine for me. (I have most of the parts for something like that already)
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Post Posted: Mon Apr 04, 2011 4:24 pm
Well, I went for a "pure" design using 74 ICs because I think it will be easier to "mass produce", and more accessible to people who do not have the knowledge nor the resources to use programmable logic.
However, the current circuit has the possible problem that if anyone builds it, it may not function properly. I've thought of using breadboards for building the prototype (all the required ICs cost about 5€ :) ), but it would be a hell of a mess, and I wonder if the parasitic capacitance of the board could affect the circuit, as I don't have either oscilloscopes and logic analyzers to "debug" it.
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Post Posted: Mon Apr 04, 2011 9:50 pm
I too prefer the idea of using the 74 series ICs for much the same reasons as you.

I was thinking of the breadboard idea as well but agree, if problems were caused by crappy wiring it may make false failure on an otherwise working design.

So perhaps a CPLD etc might be better for prototyping first, then if that works we can seriously consider the 74 circuit.

Can I get your files for circuit simulation and PCB? The PCB layout is pretty good although some tracks appear to be shorting and require some modification.

Also, what programs did you use for simulation and PCB layout?
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Post Posted: Fri Apr 08, 2011 11:22 am
This might be helpful: CPLD Paging IC (mapper) http://www.smspower.org/forums/viewtopic.php?t=9821

Implementation of a SMS mapper in a CPLD
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Post Posted: Fri Apr 08, 2011 6:07 pm
Agent24 wrote
Can I get your files for circuit simulation and PCB? The PCB layout is pretty good although some tracks appear to be shorting and require some modification.

Also, what programs did you use for simulation and PCB layout?

The software I used to draw / simulate the circuit is the well known (and extensively used in academics) MultiSim (good ol' Electronics Workbench).
Give me a couple of days and I'll post here the files. I'm very busy at the moment =P and I have to find them..

Kind regards,
CK
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Post Posted: Sat Apr 16, 2011 12:43 pm
Hey, just wondering if you found those simulation files yet?

Guess I better ask django for the PCB layout, I thought you had designed that also, but my mistake.
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Post Posted: Mon Apr 18, 2011 1:14 pm
Last edited by C3R14L.K1L4 on Thu May 12, 2011 7:34 pm; edited 2 times in total
Sorry for the delay. Here it is, hope it helps you or anyone else.

You'll need at least MultiSim version 9 to open this file. The program can't export in any other format, except .CIR (netlist, not useful).

Kind regards,
CK

EDIT: PDF removed. Latest version below.
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Post Posted: Mon Apr 18, 2011 1:30 pm
Thanks! I'll take a good look at this soon....
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Post Posted: Mon Apr 18, 2011 11:37 pm
Took a look at your file this morning, I notice there are some changes..
I assume these are new corrections\features and should be used rather than the old version?

Also wondering why your 574s have VHDL after the name, is this some custom version?

(Currently can't run the simulation actually, complains the VHDL module is not installed :( )
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Post Posted: Tue Apr 19, 2011 1:54 pm
Last edited by C3R14L.K1L4 on Tue Apr 19, 2011 4:49 pm; edited 2 times in total
Quote
Took a look at your file this morning, I notice there are some changes..
I assume these are new corrections\features and should be used rather than the old version?


You must be referring to this schematic:
http://www.smspower.org/forums/viewtopic.php?p=49939#49939

Yes, it is deprecated (very likely incorrect and inoperable... I've marked it as such now). The PDF posted at "Tue Feb 12, 2008 2:09 am" is also in the same situation, so I removed it.

Quote
Also wondering why your 574s have VHDL after the name, is this some custom version?

(Currently can't run the simulation actually, complains the VHDL module is not installed :( )

Probably because the version I was using at the time didn't have any other "virtual IC" for the 74574 model. So I chose the VHDL one. I've checked with MS 11 and mine has the model 74F574 (fast logic family), so you can replace the VHDL model with that one. When you replace the IC (double click each 574, click replace, search *574* and select a non VHDL model), don't forget to recheck the wiring, it may be totally wrong (happens here).

I can edit the file and upload it here, but it will require you to have MS 11.

EDIT: I have a feeling there is a serious fault in that circuit (forgot to check active low/high logic). Seems U6's output output must be inverted to feed U7A. I don't remember SMS/GG's mapping scheme very well, but it appears wrong...

Kind regards,
CK
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Post Posted: Tue Apr 19, 2011 4:47 pm
Last edited by C3R14L.K1L4 on Thu May 12, 2011 7:34 pm; edited 1 time in total
I've removed/marked all older schematics as "deprecated".

Here is the corrected schematic as a MultiSim 11 file and PDF. Notice the addition of U8C in the left-upper corner.

Kind regards,
CK

Note: I wish good luck building this but I hope he/she gives proper credit. I lost a good deal of time on it.

EDIT: PDF removed. Latest version below.
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Post Posted: Tue Apr 19, 2011 10:22 pm
So you think it will work or you have no idea?
I am just learning about these things, so don't fully understand the circuit yet...


Anyway, I plan to test it out on breadboard first and see what happens. Hopefully it will do something useful...

And I agree, you definitely deserve credit and much appreciation for this! Clearly a lot of time and effort has gone in (I can't say I have designed any circuits like this but I have designed a fair few board layouts so I can just imagine how 'fun' it was!)


If the breadboard version works, I'll try to finalize a PCB layout (been working on one the last 2 days, based heavily on the works of django as posted earlier in the thread (I tried contacting him about his design but got no reply, so rebuilt the thing from scratch)

I think I will need to install some jumpers\DIPswitches to allow selection between different EPROM sizes\types as they don't have identical pinouts.


That brings me to another question - do you think this design would support programming of the EEPROM in-circuit or does it only work for reading?

Obviously EPROMs can't be supported as they need 12.5v but 5v EEPROMs and Flash EEPROMs maybe - through the SMSReader? (I guess the program and hardware would probably need modification though)

(Obviously this feature is not needed, but would probably be quite useful for some, and probably more convenient all around)


But I suppose, should concentrate on getting the circuit basically working first ;)

I'll order the ICs soon, and then we can see what happens...
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Post Posted: Wed Apr 20, 2011 12:37 pm
Quote
So you think it will work or you have no idea?
I am just learning about these things, so don't fully understand the circuit yet...

I'm almost sure it will work, but there are some specifics about the cartridge slot I don't know. What I'm trying to say is, the circuit I designed follows the SMS's mapping scheme, that is, the CPU can address 4 blocks of 16 KB, where each one can come from anywhere in the external PROM. Basically, it's a simplified version of virtual memory, the circuit can be adapted to extract those blocks from anywhere you want, even from a hard drive (excluding the required implementations details for that feature ^^ )

The information I used to design the circuit comes from this site's old documentation, like a document titled "SMSARCH: A Sega Master System Cartridge Archiver". More info is available in the section "Documentation - Memory System". For instance, I assume the address range $0000-$03ff [ROM (unpaged)] does not conflict with the external cartridge's ROM (as viletim confirms above, correct me if I'm wrong).

The FCRx writting is correct, as the circuit requires the CPU to specify the exact address and operation (A2...A15 = 1, Write bit and CE bit set to zero). I'm not sure if the CE bit must be active (low, 0) to write to the FCRs. If this is wrong, correct me. The specific FCR to be written is chosen using a binary to decimal decoder so that each consecutive address following $fffc (excluding Cartridge RAM mapper control register) goes to the correspondent latch (U1...U3). FCR's decoder output Y0 can be used to implement the mapper control register, so that a possible RAM can be added (further development?).

Obviously, the mapper chooses the 16 KB external memory block according to the region of memory the CPU is addressing, consequently the page decoder section U4A uses bits A14 & A15 for this. Basically those bits are decoded to decimal and used to enable one of those FCRs (U1...U3) to switch the external's PROM page. That section only does the mapping, nothing more. Further operations done on the external PROM require the bits to Read and enable it (CE). It appears to me, know, that U5A and the R bit aren't needed to enable the PROM's output. Consequently, U5B and U7B can be removed so that the cartridge's CE bit controls directly the external PROM's OE pin. Someone correct me if this is wrong.

All the above thinking "adheres highly" to the SMS/GG's mapping scheme, I suppose... so like Mulder, "I want to believe"... ;)

I think I've explained succinctly the circuit's logic... Any question, don't be afraid to ask.

Quote
That brings me to another question - do you think this design would support programming of the EEPROM in-circuit or does it only work for reading?

Negative. This circuit only connects a PROM (please read ROM) to the system. It offers the possibility of adding the known external RAM some games has. However, there is no option for programming PROMs incircuit. You can always connect the cartridge's W pin to the PROM's (EPROM, EEPROM, etc.) W pin. However, the possibility of a program altering the PROM's contents arises. I'm not informed if there are EEPROMs programmable with 5V, which could be then altered by the system (SMS/GG) itself. Possibly dangerous, I may ask...?
Worst, how do you program a PROM incircuit from let's say, a PC. This circuit would require some form of programming logic beyond my knowledge, like a USB to PROM interface, as it's hard to find centronics/parallel port connections in these days...

To be honest, the circuit was designed to use external (programmed) PROMs =P

May SMS's Power be with you,
CK
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Post Posted: Fri Apr 22, 2011 5:52 pm
Project isn´t dead, just never had time, the parts or good equipment to make
a good double sided pcb. I try to make it in the next weeks together with
some other usefull things, but have to test them first.
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Post Posted: Sat Apr 23, 2011 12:38 am
Last edited by Agent24 on Sat Apr 23, 2011 2:17 am; edited 1 time in total
OK, well this forum just ruined my post I spent 10 minutes writing - because apparently the word "T0N3R" is not allowed (Why??) - (I was talking about PCB manufacture using laser printer\laminator etc - as far as I know there's nothing wrong with that??)


ANYWAY....

Short version is: Your PCB layout as you posted earlier has problems, eg: tracks appear to have clearance issues, also the 574s pins 11 and 1 are swapped, there are some tracks missing or wrong and it's not based on the latest version which included an extra 74LS04 and some other changes.


I will be done soon and if you want I can send you my version (I used KiCAD, not sure what you used) if you want to try it out.

I personally will be testing it out on breadboard first, just in case it doesn't work (don't want to go to the trouble making a faulty board, really)

Ps: Did you just send me a PM? I received an email saying I had been sent one, but when I checked on the forum there is nothing there.
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Post Posted: Sat Apr 23, 2011 1:48 am
Agent24 wrote
OK, well this forum just ruined my post I spent 10 minutes writing - because apparently the word "T0N3R" is not allowed (Why??) - (I was talking about PCB manufacture using laser printer\laminator etc - as far as I know there's nothing wrong with that??)


I'd guess because it's word rarely used aside from spambots.
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Post Posted: Sun May 01, 2011 10:45 pm
Well, I've ordered the ICs from Farnell, so they should arrive sometime soon, and then I can test and see what happens...

Also, I found this from user TmEE:

Quote
2 pics of my mapper. I would be using my 4Mbyte MD flashcart with it, hence it having MD compatible pinout on the cartslot on top.... I have to add SMS connector on bottom and try it out... its been like so for over a year now D:
http://www.fileden.com/files/2008/4/21/1876835/SMSmapperFront.jpg
http://www.fileden.com/files/2008/4/21/1876835/SMSmapperBack.jpg

(from http://www.smspower.org/forums/viewtopic.php?p=58127)

The schematic might prove interesting, although it seems like he never actually tried it out.
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Post Posted: Wed May 11, 2011 11:26 pm
Sorry for late reply, but I haven't received reply notifications through my email.

Agent24 wrote
Your PCB layout as you posted earlier has problems

The PCB posted by django above is very likely linked to an older schematic and therefore outdated.

Agent24 wrote
I personally will be testing it out on breadboard first, just in case it doesn't work (don't want to go to the trouble making a faulty board, really)


My point, exactly.

Agent24 wrote
Ps: Did you just send me a PM? I received an email saying I had been sent one, but when I checked on the forum there is nothing there.


I don't know if that's addressed to me :) If it is, answer is "Negative".

Agent24 wrote


I can't find his schematic, but his logic seems different from mine. He has a decoder (74139), 8-Bit Magnitude Comparator ICs (74688), a octal D Flip Flop and more ICs I can't read their references. Must serve the same purpose (implement some FCRs) as my circuit, but done in a different way. The schematic posted above should only fail on my questions regarding Sega's logic (please check my last post for further explanation). These are the following:

- I assume the address range $0000-$03ff [ROM (unpaged)] does not conflict with the external cartridge's ROM (as viletim confirms above, correct me if I'm wrong).
- I don't know if the CE pin must be active low (grounded, 0 V) when writing to the FCRs.
- The cartridge's CE pin controls directly the external PROM's OE pin.


I would appreciate if someone helps me on this.

Kind regards,
CK
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