Sega Master System and Game Gear Programmer's Guide

Version 0.00

S8-Dev Standards Committee

Table of Contents

Table of Contents

List of Figures

I.1: About this Document

I.2: Document Conventions

I.2.1: Hexadecimal and Binary Numbers

I.2.2: Bit and Byte Order

I.2.3: Reserved Bits

I.2.4: Instruction Operands

I.3: Revision History

I.4: Acknowledgements

Chapter 1: Introduction to WLA-DX

Chapter 2: Programming the Z80 Processor

Chapter 3: Memory Management

3.1.1: Run-Time Variables

3.1.2: The Stack

3.2: Understanding Paging

Chapter 4: Taking Control

4.2: The Light Phaser

4.3: Take Pause

Chapter 5: The Video Display Processor (VDP)

5.3: The Palette

5.4: Access to VRAM

5.5: Line Interrupts

Chapter 6: The Programmable Sound Generator (PSG)

Chapter 7: The FM Unit (FMU)

Chapter 8: Advanced Topics

8.1: Split-screen and Parallax Scrolling

8.2: SegaScope 3-D

8.3: Digitized Audio

8.4: Game Gear Gear-to-Gear

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

List of Figures

[To Be Completed]

[To Be Completed]

I.1 About this Document

[To Be Completed]

I.2 Document Conventions

This document uses a specific notation for hexadecimal and binary numbers, symbolic representation of instructions, and data-structure formats. Familiarity with this notation is essential to understanding this document.

I.2.1 Hexadecimal and Binary Numbers

Hexadecimal (Base 16) numbers are represented using the WLA-DX format of the "$" symbol followed by a string of hexadecimal digits (1-9 and A-F). The hexadecimal digits 'A' through 'F' will always be upper-case. A valid hexadecimal number representation would be: $C0FF.

Binary (Base 2) numbers are represented using the WLA-DX format of the "%" symbol followed by a string of binary digits (0 and 1). A valid binary number representation would be: %11100110.

I.2.2 Bit and Byte Order

Bits are numbered starting from right to left, (i.e., least-significant to most-significant.) All bytes consist of eight bits: 0 through 7.

The SMS and GG machines are both based on Zilog's Z80 microprocessor. This microprocessor is a "little-endian" machine, meaning that bytes of a word are numbered starting from the least-significant byte. As a result, the SMS and GG machines are also little-endian. The least-significant byte in a word will always be stored to memory first, at the lower address, followed by the most-significant byte at the higher address.

Diagrams of data structures in memory will have lower memory addresses towards the bottom of the page, with higher addresses growing towards the top of the page.

I.2.3 Reserved Bits

In certain register layout descriptions, various bits will be marked as "Reserved." All reserved bits are implicitly RESET (0). Software should never attempt to SET these bits (to 1). Follow the guidelines below:

Do not depend on the states of any reserved bits when testing the values of defined register bits. Mask out the reserved bits when testing.
Do not depend on the states of any reserved bits when storing them to memory or another register.
Do not depend on the ability to retain information written into any reserved bits.
Always load the reserved bits as zeros.

I.2.4 Instruction Operands

The main processor used in the SMS and GG machines is the Zilog Z80 microprocessor. The symbolic representation of instructions is taken directly from Z80 assembly language. The format is shown below:

label: mnemonic argument1, argument2

where:

A label is an identifier followed by a colon (:).
A mnemonic is a reserved name for a class of instruction opcodes which have the same function.
The operands argument1, argument2 are optional. There may be zero, one, or two arguments, depending on the instruction. When present, they are either literals, or data identifiers. The data identifiers are either reserved register names, or are assigned to data items declared elsewhere in the source file.

When two operands are present, the right operand is the source and the left is the destination.

For example:

LOOP1:  LD HL, STARTVALUE

In this example, LOOP1 is a label, LD is the mnemonic identifier for the opcode, HL is the destination operand, and STARTVALUE is the source operand.

I.3 Revision History

Version 0.00.00 (April 30, 2001): Initial version.

I.4 Acknowledgements

This reference manual could not have existed without the help of numerous people.

[To Be Completed]

Chapter 1: Introduction to WLA-DX

[To Be Completed]

Chapter 2: Programming the Z80 Processor

[To Be Completed]

Chapter 3: Memory Management

[To Be Completed]

3.1 Using RAM

[To Be Completed]

3.1.1 Run-Time Variables

[To Be Completed]

3.1.2 The Stack

[To Be Completed]

3.2 Understanding Paging

[To Be Completed]

Chapter 4: Taking Control

[To Be Completed]

4.1 Joypads

[To Be Completed]

4.2 The Light Phaser

[To Be Completed]

4.3 Take Pause

[To Be Completed]

Chapter 5: The Video Display Processor (VDP)

[To Be Completed]

5.1 Tiles

[To Be Completed]

5.2 Sprites

[To Be Completed]

5.3 The Palette

[To Be Completed]

5.4 Access to VRAM

[To Be Completed]

5.5 Line Interrupts

[To Be Completed]

Chapter 6: The Programmable Sound Generator (PSG)

[To Be Completed]

Chapter 7: The FM Unit (FMU)

[To Be Completed]

Chapter 8: Advanced Topics

[To Be Completed]

8.1 Split-screen and Parallax Scrolling

[To Be Completed]

8.2 SegaScope 3-D

[To Be Completed]

8.3 Digitized Audio

[To Be Completed]

8.4 Game Gear Gear-to-Gear

[To Be Completed]

[To Be Completed]

A

B

C

D

E

F

Frame: See Page Frame

G

H

I

Interrupt: Asynchronous event that indicates to the processor that an external device needs attention. Interrupts re-direct the normal execution flow based on the interrupt mode the processor is in when the interrupt is received. Interrupts can be enabled or disabled by software. In the SMS and GG interrupts are only sent by the Video Display Processor.
INTR: See Interrupt

J

K

L

M

N

NMI: Non-Maskable Interrupt. NMIs are interrupts that cannot be disabled by software. NMIs are generally used to indicate fatal system errors. In the SMS the Pause button is connected to the processor's NMI line.

O

P

Page: A 16KByte are of memory, typically ROM, that can be mapped in and out of processor-addressable memory space.
Page Frame: A region in main memory used for mapping pages
Page Frame Register: A register contained in a cartridge identifying which ROM page is mapped into a page frame.

Q

R

RAM: Random-Access Memory. RAM is both readable and writeable, and is used for storage of run-time variables and the stack.
Register: A data storage location inside a system device. Registers can be accessed very quickly and generally contain configuration information or the temporary results of calculations. In SMS and GG systems, the Z80, VDP, PSG, and FMU all contain their own Register Files.
Register File: A collection of registers. The general-purpose registers in the Z80 make up a single register file.
Reset, Hard: A reset achieved by powering-on the system.
Reset, Soft: A reset issued by pressing the system's Reset button.
ROM: Read-Only Memory. SMS and GG cards and cartridges use ROM for storing program code and data.

S

T

U

V

W

X

Y

Z

[To Be Completed]