Sega Master System and Game Gear Hardware Reference Manual

Version 0.00

S8-Dev Standards Committee

Table of Contents

Table of Contents

List of Figures
Figure 3.a: Generic Memory Map

Introduction
I.1: About this Document
I.2: Document Conventions
I.2.1: Hexadecimal and Binary Numbers
I.2.2: Bit and Byte Order
I.2.3: Reserved Bits
I.2.4: Instruction Operands
I.3: Revision History
I.4: Acknowledgements

Chapter 1: Architecture Overview
1.1: System Devices Overview
1.2: Summary of Sega Master System and Game Gear Differences

Chapter 2: The Z80 Processor
2.1: Z80 Architecture
2.1.1: The General-Purpose Registers
2.1.2: Memory and Input/Output Ports
2.1.3: Interrupt Mechanism
2.2: Instruction Set Summary

Chapter 3: The Memory System
3.1: BIOS ROM
3.2: RAM
3.3: Card Slot
3.4: Cartridge Slot
3.4.1: The Page Frame Registers
3.4.2: Page Frame 0
3.4.3: Page Frame 1
3.4.4: Page Frame 2
3.5: Expansion Slot

Chapter 4: The Input/Output Hub
4.1: Peripheral Ports
4.2: Pause and Reset
4.3: Configuring the Memory System

Chapter 5: The Video Display Processor (VDP)
5.1: VDP Registers
5.2: VDP Palette (CRAM)
5.2.1: The Master System Palette
5.2.2: The Game Gear Palette
5.3: VRAM

Chapter 6: The Programmable Sound Generator (PSG)

Chapter 7: The FM Unit (FMU)

Appendix A: The Z80 Instruction Set

Glossary
[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

References


List of Figures

Figure 3.a: Generic Memory Map

[To Be Completed]


Introduction

This document is a hardware reference manual for the Sega Master System (SMS) and Game Gear (GG) machines.


I.1 About this Document

The purpose of this document is to be a reference for the SMS and GG machines. This document covers the functional (logical) aspects of the SMS and GG. This document does not include electrical or mechanical specifications for the SMS and GG machines.


I.2 Document Conventions

This document uses a specific notation for hexadecimal and binary numbers, symbolic representation of instructions, and data-structure formats. Familiarity with this notation is essential to understanding this document.

I.2.1 Hexadecimal and Binary Numbers

Hexadecimal (Base 16) numbers are represented using the WLA-DX format of the "$" symbol followed by a string of hexadecimal digits (1-9 and A-F). The hexadecimal digits 'A' through 'F' will always be upper-case. A valid hexadecimal number representation would be: $C0FF.

Binary (Base 2) numbers are represented using the WLA-DX format of the "%" symbol followed by a string of binary digits (0 and 1). A valid binary number representation would be: %11100110.

I.2.2 Bit and Byte Order

Bits are numbered starting from right to left, (i.e., least-significant to most-significant.) All bytes consist of eight bits: 0 through 7.

The SMS and GG machines are both based on Zilog's Z80 microprocessor. This microprocessor is a "little-endian" machine, meaning that bytes of a word are numbered starting from the least-significant byte. As a result, the SMS and GG machines are also little-endian. The least-significant byte in a word will always be stored to memory first, at the lower address, followed by the most-significant byte at the higher address.

Diagrams of data structures in memory will have lower memory addresses towards the bottom of the page, with higher addresses growing towards the top of the page.

I.2.3 Reserved Bits

In certain register layout descriptions, various bits will be marked as "Reserved." All reserved bits are implicitly RESET (0). Software should never attempt to SET these bits (to 1). Follow the guidelines below:

  1. Do not depend on the states of any reserved bits when testing the values of defined register bits. Mask out the reserved bits when testing.
  2. Do not depend on the states of any reserved bits when storing them to memory or another register.
  3. Do not depend on the ability to retain information written into any reserved bits.
  4. Always load the reserved bits as zeros.

I.2.4 Instruction Operands

The main processor used in the SMS and GG machines is the Zilog Z80 microprocessor. The symbolic representation of instructions is taken directly from Z80 assembly language. The format is shown below:

label: mnemonic argument1, argument2

where:

When two operands are present, the right operand is the source and the left is the destination.

For example:

LOOP1:  LD HL, STARTVALUE

In this example, LOOP1 is a label, LD is the mnemonic identifier for the opcode, HL is the destination operand, and STARTVALUE is the source operand.


I.3 Revision History

Version 0.00 (April 30, 2001): Initial version.


I.4 Acknowledgements

This reference manual could not have existed without the help of numerous people.

[To Be Completed]


Chapter 1: Architecture Overview

The Sega Master System (SMS) and Game Gear (GG) are 8-bit machines based off of Zilog's Z80 microprocessor. These systems each contain 8 KBytes of RAM and typically use up to 512 KByte ROM cartridges complete with on-board paging logic used to map memory into the Z80's 64KByte addressable memory space. The machines contain a sprite-based video display processor derived from the Texas Instrument's TMS9918/9928 processor and a programmable sound generator derived from the Texas Instrument's SN76489. The Sega Master System also includes two peripheral ports used for connecting devices such as joysticks or light-guns to the system. The Game Gear contains only one peripheral port, with the system's built-in four-direction, two-button controller permanently connected. The video, sound, and peripheral port services are all accessible to software through system input/output (I/O) ports.

[To Be Completed]


1.1 System Devices Overview

The components of the SMS and GG machines are:

[To Be Completed]


1.2 Summary of Sega Master System and Game Gear Differences

[To Be Completed]


Chapter 2: The Z80 Processor

[To Be Completed]


2.1 Z80 Architecture

[To Be Completed]

2.1.1 The General-Purpose Registers

[To Be Completed]

2.1.2 Memory and Input/Output Ports

[To Be Completed]

2.1.3 Interrupt Mechanism

[To Be Completed]


2.2 Instruction Set Summary

[To Be Completed]


Chapter 3: The Memory System

[To Be Completed]

AddressesRegion
$0000 - $BFFFBIOS ROM or External Memory
$C000 - $DFFFRAM
$E000 - $FFFFRAM (Mirror)
Figure 3.a: Generic Memory Map


3.1 BIOS ROM

[To Be Completed]


3.2 RAM

RAM exists between addresses $C000 and $FFFF. This region is broken into two 8KByte blocks, one from addresses $C000 through $DFFF, and the other from addresses $E000 through $FFFF. The first block is actual program RAM. This area exists as an 8KByte block of RAM in SMS and GG systems. The second area is a mirror of program RAM.

[To Be Completed]


3.3 Card Slot

[To Be Completed]


3.4 Cartridge Slot

Cartridges generally divide the area of memory from addresses $0000 through $BFFF is into three 16KByte regions called
Page Frames, (or simply Frames). A single 16KByte memory Page is mapped into each of the frames. A memory page may be simultaneously mapped into more than one page frame.

[To Be Completed]

3.4.1 The Page Frame Registers

The page frame registers are mapped to the last four bytes of RAM region ([$FFFB..$FFFF]). Because this area is a mirror of RAM, this mapping has important implications for memory at addresses $DFFB through $DFFF.
  1. Writing to [$DFFB..$DFFF] only affects RAM. The page frame registers are not affected.
  2. Writing to a page frame register also writes to the corresponding RAM byte.
  3. Reading [$DFFB..$DFFF] returns the last value written to either that byte or the corresponding page frame register.
  4. Reading the page frame register returns the last value written to RAM, (including writes to RAM that occurred due to writing to the page frame register.)

In general, it is probably best to leave the RAM at $DFFB through $DFFF alone, as writing to a page frame register has the side-effect of modifying this memory.

[To Be Completed]

3.4.2 Page Frame 0

Page Frame 0 consists of addresses $0000 through $3FFF. Mapping a memory page into this frame is controlled by page frame register $FFFD.

[To Be Completed]

3.4.3 Page Frame 1

Page Frame 1 consists of addresses $4000 through $7FFF. Mapping a page into this frame is controlled by page frame register $FFFE.

[To Be Completed]

3.4.4 Page Frame 2

Page Frame 2 consists of addresses $8000 through $BFFF. Mapping a page into this frame is controlled by page frame register $FFFF. Additionally, one of two auxiliary pages of memory can be mapped into this frame using page frame register $FFFC. In SMS and GG systems, these auxiliary pages are typically battery backed-up RAM.

[To Be Completed]


3.5 Expansion Slot

[To Be Completed]


Chapter 4: The Input/Output Hub

[To Be Completed]


4.1 Peripheral Ports

[To Be Completed]

4.2 Pause and Reset

[To Be Completed]

4.3 Configuring the Memory System

[To Be Completed]

Chapter 5: The Video Display Processor (VDP)

[To Be Completed]


5.1 VDP Registers

[To Be Completed]


5.2 VDP Palette (CRAM)

[To Be Completed]

5.2.1 The Master System Palette

[To Be Completed]

5.2.2 The Game Gear Palette

[To Be Completed]


5.3 VRAM

[To Be Completed]


Chapter 6: The Programmable Sound Generator (PSG)

[To Be Completed]


Chapter 7: The FM Unit (FMU)

[To Be Completed]


Appendix A: The Z80 Instruction Set

[To Be Completed]

Object CodeInstructionFlagsClock Cycles
SZHP/ONC
00 NOP       
01 yyyy LD BC, data16       
02 LD (BC), A       
03 INC BC       
04 INC B SZHOV0 
05 DEC B SZHOV1 
06 yy LD B, data       
07 RLCA   0 0C
08 EX AF, AF'       
09 ADD HL,BC   ? 0C
0A LD A,(BC)       
0B DEC BC       
0C INC C SZHOV0 
0D DEC C SZHOV1 
0E yy LD C, data       
0F RRCA   Z 0C
10 disp-2 DJNZ disp       
11 yyyy LD DE, data16       
12 LD (DE), A       
13 INC DE       
14 INC D SZHOV0 
15 DEC D SZHOV1 
16 yy LD D, data       
17 RLA   0 0C
18 disp-2 JR disp       
19 ADD HL,DE   ? 0C
1A LD A, (DE)       
1B DEC DE       
1C INC E SZHOV0 
1D DEC E SZHOV1 
1E yy LD E, data       
1F RRA   0 0C
20 disp-2 JR NZ, disp       
21 yyyy LD HL, data16       
22 ppqq LD (addr), HL       
23 INC HL       
24 INC H SZHOV0 
25 DEC H SZHOV1 
26 yy LD H, data       
27 DAA SZHP C
28 disp-2 JR Z, disp       
29 ADD HL, HL   ? 0C
2A ppqq LD HL, (addr)       
2B DEC HL       
2C INC L SZHOV0 
2D DEC L SZHOV1 
2E LD L, data       
2F CPL   1 1 
30 disp-2 JR NC, disp       
31 yyyy LD SP, data16       
32 ppqq LD (addr), A       
33 INC SP       
34 INC (HL) SZHOV0 
35 DEC (HL) SZHOV1 
36 yy LD (HL), data       
37 SCF   0 01
38 JR C, disp       
39 ADD HL, SP   ? 0C
3A ppqq LD A, (addr)       
3B DEC SP       
3C INC A SZHOV0 
3D DEC A SZHOV1 
3E yy LD A, data       
3F CCF   ? 0C
40sss LD B, reg       
46 LD B, (HL)       
41sss LD C, reg       
4E LD C, (HL)       
50sss LD D, reg       
56 LD D, (HL)       
51sss LD E, reg       
5E LD E, (HL)       
60sss LD H, reg       
66 LD H, (HL)       
61sss LD L, reg       
6E LD L, (HL)       
70sss LD (HL), reg       
76 HALT       
71sss LD A, reg       
7E LD A, (HL)       
80sss ADD A, reg SZHOV0C
86 ADD A, (HL) SZHOV0C
81sss ADC A, reg SZHOV0C
8E ADC A, (HL) SZHOV0C
90sss SUB A, reg SZHOV1C
96 SUB A, (HL) SZHOV1C
91sss SBC A, reg SZHOV1C
9E SBC A, (HL) SZHOV1C
A0sss AND A, reg SZ1P00
A6 AND A, (HL) SZ1P00
A1sss XOR A, reg SZ1P00
AE XOR A, (HL) SZ1P00
B0sss OR A, reg SZ1P00
B6 OR A, (HL) SZ1P00
B1sss CP A, reg SZHOV1C
BE CP A, (HL) SZHOV1C
C0 RET NZ       
C1 POP BC       
C2 ppqq JP NZ, addr       
C3 ppqq JP addr       
C4 ppqq CALL NZ, addr       
C5 PUSH BC       
C6 yy ADD A, data SZHOV0C
C7 RST 00h       
C8 RET Z       
C9 RET       
CA ppqq JP Z, addr       
CB 0 0rrr RLC reg SZ0P0C
CB 06 RLC (HL) SZ0P0C
CB 0 1rrr RRC reg SZ0P0C
CB 0E RRC (HL) SZ0P0C
CB 1 0rrr RL reg SZ0P0C
CB 16 RL (HL) SZ0P0C
CB 1 1rrr RR reg SZ0P0C
CB 1E RR (HL) SZ0P0C
CB 2 0rrr SLA reg SZ0P0C
CB 26 SLA (HL) SZ0P0C
CB 2 1rrr SRA reg SZ0P0C
CB 2E SRA (HL) SZ0P0C
CB 3 1rrr SRL reg SZ0P0C
CB 3E SRL (HL) SZ0P0C
CB 01bbbrrr BIT b, reg ?Z1?0 
CB 01bbb110 BIT b, (HL) ?Z1?0 
CB 10bbbrrr RES b, reg       
CB 10bbb110 RES b, (HL)       
CB 11bbbrrr SET b, reg       
CB 11bbb110 SET b, (HL)       
CC ppqq CALL Z, addr       
CD ppqq CALL addr       
CE yy ADC A, data SZHOV0C
CF RST 08h       
D0 RET NC       
D1 POP DE       
D2 ppqq JP NC, addr       
D3 yy OUT (port), A       
D4 ppqq CALL NC, addr       
D5 PUSH DE       
D6 yy SUB A, data SZHOV1C
D7 RST 10h       
D8 RET C       
D9 EXX       
DA ppqq JP C, addr       
DB yy IN A, (port)       
DC ppqq CALL C, addr       
DD 00xx 9 ADD IX, rp   ? 0C
DD 21 yyyy LD IX, data16       
DD 22 ppqq LD (addr), IX       
DD 23 INC IX       
DD 2A LD IX, (addr)       
DD 2B DEC IX       
DD 34 disp INC (IX+disp) SZHOV0 
DD 35 disp DEC (IX+disp) SZHOV0 
DD 36 disp yy LD (IX+disp), data       
DD 01ddd110 dispLD reg, (IX+disp)       
DD 7 0sss disp LD (IX+disp), reg       
DD 86 disp ADD A, (IX+disp) SZHOV0C
DD 8E disp ADC A, (IX+disp) SZHOV0C
DD 96 disp SUB A, (IX+disp) SZHOV1C
DD 9E disp SBC A, (IX+disp) SZHOV1C
DD A6 disp AND A, (IX+disp) SZ1P00
DD AE disp XOR A, (IX+disp) SZ1P00
DD B6 disp OR A, (IX+disp) SZ1P00
DD BE disp CP A, (IX+disp) SZHOV1C
DD CB disp 06 RLC A, (IX+disp) SZ0P0C
DD CB disp 0E RRC A, (IX+disp) SZ0P0C
DD CB disp 16 RL A, (IX+disp) SZ0P0C
DD CB disp 1E RR A, (IX+disp) SZ0P0C
DD CB disp 26 SLA A, (IX+disp) SZ0P0C
DD CB disp 2E SRA A, (IX+disp) SZ0P0C
DD CB disp 3E SRL A, (IX+disp) SZ0P0C
DD CB disp 01bbb110BIT b, (IX+disp) ?Z1?0 
DD CB disp 10bbb110RES b, (IX+disp)       
DD CB disp 11bbb110SET b, (IX+disp)       
DD E1 POP IX       
DD E3 EX (SP), IX       
DD E5 PUSH IX       
DD E9 JP (IX)       
DD F9 LD SP, IX       
DE yy SBC A, data SZHOV1C
DF RST 18h       
E0 RET PO       
E1 POP HL       
E2 ppqq JP PO, addr       
E3 EX (SP), HL       
E4 ppqq CALL PO, addr       
E5 PUSH HL       
E6 yy AND data SZ1P00
E7 RST 20h       
E8 RET PE       
E9 JP (HL)       
EA ppqq JP PE, addr       
EB EX DE, HL       
EC ppqq CALL PE, addr       
ED 01ddd000 IN reg,(C) SZHP0 
ED 01sss001 OUT (C), reg       
ED 01xx 2 SBC HL, rp SZ?OV1C
ED 01xx 3 ppqq LD (addr), rp       
ED 44 NEG SZHOV1C
ED 45 RETN       
ED 47 LD I, A       
ED 01xx A ADC HL, rp SZ?OV0C
ED 01xx B ppqq LD rp, (addr)       
ED 4D RETI       
ED 4F LD R, A       
ED 56 IM 1       
ED 57 LD A, I SZ0I0 
ED 5F LD A, R SZ0I0 
ED 67 RRD SZ0P0 
ED 6F RLD SZ0P0 
ED A0 LDI   0H0 
ED A1 CPI SZHBC!=01 
ED A2 INI ?Z??1 
ED A3 OUTI ?Z??1 
ED A8 LDD   0H0 
ED A9 CPD SZHBC!=01 
ED AA IND ?Z??1 
ED AB OUTD ?Z??1 
ED B0 LDIR   000 
ED B1 CPIR SZHBC!=01 
ED B2 INIR ?1??1 
ED B3 OTIR ?1??1 
ED B8 LDDR   000 
ED B9 CPDR SZHBC!=01 
ED BA INDR ?1??1 
ED BB OTDR ?1??1 
EE yy XOR A, DATA SZ1P00
EF RST 28h       
F0 RET P       
F1 POP AF       
F2 ppqq JP P, addr       
F3 DI       
F4 ppqq CALL P, addr       
F5 PUSH AF       
F6 yy OR A, data SZ1P00
F7 RST 30h       
F8 RET M       
F9 LD SP, HL       
FA ppqq JP M, addr       
FB EI       
FC ppqq CALL M, addr       
FD 00xx 9 ADD IY, rp   ? 0C
FD 21 yyyy LD IY, data16       
FD 22 ppqq LD (addr), IY       
FD 23 INC IY       
FD 2A LD IY, (addr)       
FD 2B DEC IY       
FD 34 disp INC (IY+disp) SZHOV0 
FD 35 disp DEC (IY+disp) SZHOV0 
FD 36 disp yy LD (IY+disp), data       
FD 01ddd110 dispLD reg, (IY+disp)       
FD 7 0sss disp LD (IY+disp), reg       
FD 86 disp ADD A, (IY+disp) SZHOV0C
FD 8E disp ADC A, (IY+disp) SZHOV0C
FD 96 disp SUB A, (IY+disp) SZHOV1C
FD 9E disp SBC A, (IY+disp) SZHOV1C
FD A6 disp AND A, (IY+disp) SZ1P00
FD AE disp XOR A, (IY+disp) SZ1P00
FD B6 disp OR A, (IY+disp) SZ1P00
FD BE disp CP A, (IY+disp) SZHOV1C
FD CB disp 06 RLC A, (IY+disp) SZ0P0C
FD CB disp 0E RRC A, (IY+disp) SZ0P0C
FD CB disp 16 RL A, (IY+disp) SZ0P0C
FD CB disp 1E RR A, (IY+disp) SZ0P0C
FD CB disp 26 SLA A, (IY+disp) SZ0P0C
FD CB disp 2E SRA A, (IY+disp) SZ0P0C
FD CB disp 3E SRL A, (IY+disp) SZ0P0C
FD CB disp 01bbb110BIT b, (IY+disp) ?Z1?0 
FD CB disp 10bbb110RES b, (IY+disp)       
FD CB disp 11bbb110SET b, (IY+disp)       
FD E1 POP IY       
FD E3 EX (SP), IY       
FD E5 PUSH IY       
FD E9 JP (IY)       
FD F9 LD SP, IY       
FE yy CP A, data SZHOV1C
FF RST 38h       

Glossary

[To Be Completed]


A



B



C



D



E



F


Frame
See Page Frame


G



H



I


Interrupt
Asynchronous event that indicates to the processor that an external device needs attention. Interrupts re-direct the normal execution flow based on the interrupt mode the processor is in when the interrupt is received. Interrupts can be enabled or disabled by software. In the SMS and GG interrupts are only sent by the Video Display Processor.

INTR
See Interrupt


J



K



L



M



N


NMI
Non-Maskable Interrupt. NMIs are interrupts that cannot be disabled by software. NMIs are generally used to indicate fatal system errors. In the SMS the Pause button is connected to the processor's NMI line.


O



P


Page
A 16KByte are of memory, typically ROM, that can be mapped in and out of processor-addressable memory space.

Page Frame
A region in main memory used for mapping pages

Page Frame Register
A register contained in a cartridge identifying which ROM page is mapped into a page frame.


Q



R


RAM
Random-Access Memory. RAM is both readable and writeable, and is used for storage of run-time variables and the stack.

Register
A data storage location inside a system device. Registers can be accessed very quickly and generally contain configuration information or the temporary results of calculations. In SMS and GG systems, the Z80, VDP, PSG, and FMU all contain their own Register Files.

Register File
A collection of registers. The general-purpose registers in the Z80 make up a single register file.

Reset, Hard
A reset achieved by powering-on the system.

Reset, Soft
A reset issued by pressing the system's Reset button.

ROM
Read-Only Memory. SMS and GG cards and cartridges use ROM for storing program code and data.


S



T



U



V



W



X



Y



Z



References

[To Be Completed]