| Table of Contents |
| List of Figures |
Figure 3.a: Generic Memory Map
[To Be Completed]
| Introduction |
This document is a hardware reference manual for the Sega Master System (SMS) and Game Gear (GG) machines.
Binary (Base 2) numbers are represented using the WLA-DX format of the "%"
symbol followed by a string of binary digits (0 and 1). A valid binary number
representation would be: %11100110.
The SMS and GG machines are both based on Zilog's Z80 microprocessor. This
microprocessor is a "little-endian" machine, meaning that bytes of a word
are numbered starting from the least-significant byte. As a result,
the SMS and GG machines are also little-endian. The least-significant byte
in a word will always be stored to memory first, at the lower address, followed
by the most-significant byte at the higher address.
Diagrams of data structures in memory will have lower memory addresses
towards the bottom of the page, with higher addresses growing towards the top
of the page.
where:
For example:
In this example, LOOP1 is a label, LD is the mnemonic identifier for the
opcode, HL is the destination operand, and STARTVALUE is the source operand.
The Sega Master System (SMS) and Game Gear (GG) are 8-bit machines based off of
Zilog's Z80 microprocessor. These systems each contain 8 KBytes of RAM and
typically use up to 512 KByte ROM cartridges complete with on-board paging
logic used to map memory into the Z80's 64KByte addressable memory space.
The machines contain a sprite-based video display processor derived from the
Texas Instrument's TMS9918/9928 processor and a programmable sound generator
derived from the Texas Instrument's SN76489. The Sega Master System also
includes two peripheral ports used for connecting devices such as joysticks or
light-guns to the system. The Game Gear contains only one peripheral port,
with the system's built-in four-direction, two-button controller permanently
connected. The video, sound, and peripheral port services are all accessible
to software through system input/output (I/O) ports.
[To Be Completed]
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In general, it is probably best to leave the RAM at $DFFB through $DFFF alone,
as writing to a page frame register has the side-effect of modifying this
memory.
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I.1 About this Document
The purpose of this document is to be a reference for the SMS and GG machines.
This document covers the functional (logical) aspects of the SMS and GG. This
document does not include electrical or mechanical specifications for the
SMS and GG machines.
I.2 Document Conventions
This document uses a specific notation for hexadecimal and binary numbers,
symbolic representation of instructions, and data-structure formats.
Familiarity with this notation is essential to understanding this document.I.2.1 Hexadecimal and Binary Numbers
Hexadecimal (Base 16) numbers are represented using the WLA-DX format of the
"$" symbol followed by a string of hexadecimal digits (1-9 and A-F). The
hexadecimal digits 'A' through 'F' will always be upper-case. A valid
hexadecimal number representation would be: $C0FF.I.2.2 Bit and Byte Order
Bits are numbered starting from right to left, (i.e., least-significant to
most-significant.) All bytes consist of eight bits: 0 through 7.I.2.3 Reserved Bits
In certain register layout descriptions, various bits will be marked as
"Reserved." All reserved bits are implicitly RESET (0). Software should
never attempt to SET these bits (to 1). Follow the guidelines below:
I.2.4 Instruction Operands
The main processor used in the SMS and GG machines is the Zilog Z80
microprocessor. The symbolic representation of instructions is taken directly
from Z80 assembly language. The format is shown below:
When two operands are present, the right operand is the source and the left
is the destination.LOOP1: LD HL, STARTVALUE
I.3 Revision History
Version 0.00 (April 30, 2001): Initial version.
Chapter 1: Architecture Overview
1.1 System Devices Overview
The components of the SMS and GG machines are:
[To Be Completed]
1.2 Summary of Sega Master System and Game Gear Differences
[To Be Completed]
Chapter 2: The Z80
Processor
2.1 Z80 Architecture
[To Be Completed]2.1.1 The General-Purpose Registers
[To Be Completed]2.1.2 Memory and Input/Output Ports
[To Be Completed]
Chapter 3: The Memory
System
Figure 3.a: Generic Memory Map
Addresses Region
$0000 - $BFFF BIOS ROM or External Memory
$C000 - $DFFF RAM
$E000 - $FFFF RAM (Mirror)
3.1 BIOS ROM
[To Be Completed]
3.2 RAM
RAM exists between addresses $C000 and $FFFF. This region
is broken into two 8KByte blocks, one from addresses $C000 through $DFFF,
and the other from addresses $E000 through $FFFF. The first block is
actual program RAM. This area exists as an 8KByte block of RAM in SMS and GG
systems. The second area is a mirror of program RAM.
3.3 Card Slot
[To Be Completed]
3.4 Cartridge Slot
Cartridges generally divide the area of memory from addresses $0000 through
$BFFF is into three 16KByte regions called
Page Frames, (or simply Frames). A single 16KByte memory
Page is mapped into each of the frames.
A memory page may be simultaneously mapped into more than one page frame.3.4.1 The Page Frame Registers
The page frame registers are mapped to the last four bytes of
RAM region ([$FFFB..$FFFF]). Because this area is a mirror of RAM, this
mapping has important implications for memory at addresses $DFFB through
$DFFF.
3.4.2 Page Frame 0
Page Frame 0 consists of addresses $0000 through $3FFF. Mapping a memory
page into this frame is controlled by
page frame register $FFFD.3.4.3 Page Frame 1
Page Frame 1 consists of addresses $4000 through $7FFF. Mapping a page
into this frame is controlled by
page frame register $FFFE.3.4.4 Page Frame 2
Page Frame 2 consists of addresses $8000 through $BFFF. Mapping a page
into this frame is controlled by
page frame register $FFFF. Additionally, one of two auxiliary
pages of memory can be mapped into this frame using page frame register $FFFC.
In SMS and GG systems, these auxiliary pages are typically battery backed-up
RAM.
Chapter 4: The Input/Output
Hub
4.1 Peripheral Ports
[To Be Completed]
4.2 Pause and Reset
[To Be Completed]
4.3 Configuring the Memory System
[To Be Completed]
Chapter 5: The Video
Display Processor (VDP)
5.1 VDP Registers
[To Be Completed]
5.2 VDP Palette (CRAM)
[To Be Completed]5.2.1 The Master System Palette
[To Be Completed]
Chapter 6: The
Programmable Sound Generator (PSG)
Chapter 7: The FM Unit
(FMU)
Appendix A: The Z80
Instruction Set
Object Code Instruction Flags Clock Cycles
S Z H P/O N C
00 NOP            
01 yyyy LD BC, data16            
02 LD (BC), A            
03 INC BC            
04 INC B S Z H OV 0  
05 DEC B S Z H OV 1  
06 yy LD B, data            
07 RLCA     0   0 C
08 EX AF, AF'            
09 ADD HL,BC     ?   0 C
0A LD A,(BC)            
0B DEC BC            
0C INC C S Z H OV 0  
0D DEC C S Z H OV 1  
0E yy LD C, data            
0F RRCA     Z   0 C
10 disp-2 DJNZ disp            
11 yyyy LD DE, data16            
12 LD (DE), A            
13 INC DE            
14 INC D S Z H OV 0  
15 DEC D S Z H OV 1  
16 yy LD D, data            
17 RLA     0   0 C
18 disp-2 JR disp            
19 ADD HL,DE     ?   0 C
1A LD A, (DE)            
1B DEC DE            
1C INC E S Z H OV 0  
1D DEC E S Z H OV 1  
1E yy LD E, data            
1F RRA     0   0 C
20 disp-2 JR NZ, disp            
21 yyyy LD HL, data16            
22 ppqq LD (addr), HL            
23 INC HL            
24 INC H S Z H OV 0  
25 DEC H S Z H OV 1  
26 yy LD H, data            
27 DAA S Z H P   C
28 disp-2 JR Z, disp            
29 ADD HL, HL     ?   0 C
2A ppqq LD HL, (addr)            
2B DEC HL            
2C INC L S Z H OV 0  
2D DEC L S Z H OV 1  
2E LD L, data            
2F CPL     1   1  
30 disp-2 JR NC, disp            
31 yyyy LD SP, data16            
32 ppqq LD (addr), A            
33 INC SP            
34 INC (HL) S Z H OV 0  
35 DEC (HL) S Z H OV 1  
36 yy LD (HL), data            
37 SCF     0   0 1
38 JR C, disp            
39 ADD HL, SP     ?   0 C
3A ppqq LD A, (addr)            
3B DEC SP            
3C INC A S Z H OV 0  
3D DEC A S Z H OV 1  
3E yy LD A, data            
3F CCF     ?   0 C
40sss LD B, reg            
46 LD B, (HL)            
41sss LD C, reg            
4E LD C, (HL)            
50sss LD D, reg            
56 LD D, (HL)            
51sss LD E, reg            
5E LD E, (HL)            
60sss LD H, reg            
66 LD H, (HL)            
61sss LD L, reg            
6E LD L, (HL)            
70sss LD (HL), reg            
76 HALT            
71sss LD A, reg            
7E LD A, (HL)            
80sss ADD A, reg S Z H OV 0 C
86 ADD A, (HL) S Z H OV 0 C
81sss ADC A, reg S Z H OV 0 C
8E ADC A, (HL) S Z H OV 0 C
90sss SUB A, reg S Z H OV 1 C
96 SUB A, (HL) S Z H OV 1 C
91sss SBC A, reg S Z H OV 1 C
9E SBC A, (HL) S Z H OV 1 C
A0sss AND A, reg S Z 1 P 0 0
A6 AND A, (HL) S Z 1 P 0 0
A1sss XOR A, reg S Z 1 P 0 0
AE XOR A, (HL) S Z 1 P 0 0
B0sss OR A, reg S Z 1 P 0 0
B6 OR A, (HL) S Z 1 P 0 0
B1sss CP A, reg S Z H OV 1 C
BE CP A, (HL) S Z H OV 1 C
C0 RET NZ            
C1 POP BC            
C2 ppqq JP NZ, addr            
C3 ppqq JP addr            
C4 ppqq CALL NZ, addr            
C5 PUSH BC            
C6 yy ADD A, data S Z H OV 0 C
C7 RST 00h            
C8 RET Z            
C9 RET            
CA ppqq JP Z, addr            
CB 0 0rrr RLC reg S Z 0 P 0 C
CB 06 RLC (HL) S Z 0 P 0 C
CB 0 1rrr RRC reg S Z 0 P 0 C
CB 0E RRC (HL) S Z 0 P 0 C
CB 1 0rrr RL reg S Z 0 P 0 C
CB 16 RL (HL) S Z 0 P 0 C
CB 1 1rrr RR reg S Z 0 P 0 C
CB 1E RR (HL) S Z 0 P 0 C
CB 2 0rrr SLA reg S Z 0 P 0 C
CB 26 SLA (HL) S Z 0 P 0 C
CB 2 1rrr SRA reg S Z 0 P 0 C
CB 2E SRA (HL) S Z 0 P 0 C
CB 3 1rrr SRL reg S Z 0 P 0 C
CB 3E SRL (HL) S Z 0 P 0 C
CB 01bbbrrr BIT b, reg ? Z 1 ? 0  
CB 01bbb110 BIT b, (HL) ? Z 1 ? 0  
CB 10bbbrrr RES b, reg            
CB 10bbb110 RES b, (HL)            
CB 11bbbrrr SET b, reg            
CB 11bbb110 SET b, (HL)            
CC ppqq CALL Z, addr            
CD ppqq CALL addr            
CE yy ADC A, data S Z H OV 0 C
CF RST 08h            
D0 RET NC            
D1 POP DE            
D2 ppqq JP NC, addr            
D3 yy OUT (port), A            
D4 ppqq CALL NC, addr            
D5 PUSH DE            
D6 yy SUB A, data S Z H OV 1 C
D7 RST 10h            
D8 RET C            
D9 EXX            
DA ppqq JP C, addr            
DB yy IN A, (port)            
DC ppqq CALL C, addr            
DD 00xx 9 ADD IX, rp     ?   0 C
DD 21 yyyy LD IX, data16            
DD 22 ppqq LD (addr), IX            
DD 23 INC IX            
DD 2A LD IX, (addr)            
DD 2B DEC IX            
DD 34 disp INC (IX+disp) S Z H OV 0  
DD 35 disp DEC (IX+disp) S Z H OV 0  
DD 36 disp yy LD (IX+disp), data            
DD 01ddd110 disp LD reg, (IX+disp)            
DD 7 0sss disp LD (IX+disp), reg            
DD 86 disp ADD A, (IX+disp) S Z H OV 0 C
DD 8E disp ADC A, (IX+disp) S Z H OV 0 C
DD 96 disp SUB A, (IX+disp) S Z H OV 1 C
DD 9E disp SBC A, (IX+disp) S Z H OV 1 C
DD A6 disp AND A, (IX+disp) S Z 1 P 0 0
DD AE disp XOR A, (IX+disp) S Z 1 P 0 0
DD B6 disp OR A, (IX+disp) S Z 1 P 0 0
DD BE disp CP A, (IX+disp) S Z H OV 1 C
DD CB disp 06 RLC A, (IX+disp) S Z 0 P 0 C
DD CB disp 0E RRC A, (IX+disp) S Z 0 P 0 C
DD CB disp 16 RL A, (IX+disp) S Z 0 P 0 C
DD CB disp 1E RR A, (IX+disp) S Z 0 P 0 C
DD CB disp 26 SLA A, (IX+disp) S Z 0 P 0 C
DD CB disp 2E SRA A, (IX+disp) S Z 0 P 0 C
DD CB disp 3E SRL A, (IX+disp) S Z 0 P 0 C
DD CB disp 01bbb110 BIT b, (IX+disp) ? Z 1 ? 0  
DD CB disp 10bbb110 RES b, (IX+disp)            
DD CB disp 11bbb110 SET b, (IX+disp)            
DD E1 POP IX            
DD E3 EX (SP), IX            
DD E5 PUSH IX            
DD E9 JP (IX)            
DD F9 LD SP, IX            
DE yy SBC A, data S Z H OV 1 C
DF RST 18h            
E0 RET PO            
E1 POP HL            
E2 ppqq JP PO, addr            
E3 EX (SP), HL            
E4 ppqq CALL PO, addr            
E5 PUSH HL            
E6 yy AND data S Z 1 P 0 0
E7 RST 20h            
E8 RET PE            
E9 JP (HL)            
EA ppqq JP PE, addr            
EB EX DE, HL            
EC ppqq CALL PE, addr            
ED 01ddd000 IN reg,(C) S Z H P 0  
ED 01sss001 OUT (C), reg            
ED 01xx 2 SBC HL, rp S Z ? OV 1 C
ED 01xx 3 ppqq LD (addr), rp            
ED 44 NEG S Z H OV 1 C
ED 45 RETN            
ED 47 LD I, A            
ED 01xx A ADC HL, rp S Z ? OV 0 C
ED 01xx B ppqq LD rp, (addr)            
ED 4D RETI            
ED 4F LD R, A            
ED 56 IM 1            
ED 57 LD A, I S Z 0 I 0  
ED 5F LD A, R S Z 0 I 0  
ED 67 RRD S Z 0 P 0  
ED 6F RLD S Z 0 P 0  
ED A0 LDI     0 H 0  
ED A1 CPI S Z H BC!=0 1  
ED A2 INI ? Z ? ? 1  
ED A3 OUTI ? Z ? ? 1  
ED A8 LDD     0 H 0  
ED A9 CPD S Z H BC!=0 1  
ED AA IND ? Z ? ? 1  
ED AB OUTD ? Z ? ? 1  
ED B0 LDIR     0 0 0  
ED B1 CPIR S Z H BC!=0 1  
ED B2 INIR ? 1 ? ? 1  
ED B3 OTIR ? 1 ? ? 1  
ED B8 LDDR     0 0 0  
ED B9 CPDR S Z H BC!=0 1  
ED BA INDR ? 1 ? ? 1  
ED BB OTDR ? 1 ? ? 1  
EE yy XOR A, DATA S Z 1 P 0 0
EF RST 28h            
F0 RET P            
F1 POP AF            
F2 ppqq JP P, addr            
F3 DI            
F4 ppqq CALL P, addr            
F5 PUSH AF            
F6 yy OR A, data S Z 1 P 0 0
F7 RST 30h            
F8 RET M            
F9 LD SP, HL            
FA ppqq JP M, addr            
FB EI            
FC ppqq CALL M, addr            
FD 00xx 9 ADD IY, rp     ?   0 C
FD 21 yyyy LD IY, data16            
FD 22 ppqq LD (addr), IY            
FD 23 INC IY            
FD 2A LD IY, (addr)            
FD 2B DEC IY            
FD 34 disp INC (IY+disp) S Z H OV 0  
FD 35 disp DEC (IY+disp) S Z H OV 0  
FD 36 disp yy LD (IY+disp), data            
FD 01ddd110 disp LD reg, (IY+disp)            
FD 7 0sss disp LD (IY+disp), reg            
FD 86 disp ADD A, (IY+disp) S Z H OV 0 C
FD 8E disp ADC A, (IY+disp) S Z H OV 0 C
FD 96 disp SUB A, (IY+disp) S Z H OV 1 C
FD 9E disp SBC A, (IY+disp) S Z H OV 1 C
FD A6 disp AND A, (IY+disp) S Z 1 P 0 0
FD AE disp XOR A, (IY+disp) S Z 1 P 0 0
FD B6 disp OR A, (IY+disp) S Z 1 P 0 0
FD BE disp CP A, (IY+disp) S Z H OV 1 C
FD CB disp 06 RLC A, (IY+disp) S Z 0 P 0 C
FD CB disp 0E RRC A, (IY+disp) S Z 0 P 0 C
FD CB disp 16 RL A, (IY+disp) S Z 0 P 0 C
FD CB disp 1E RR A, (IY+disp) S Z 0 P 0 C
FD CB disp 26 SLA A, (IY+disp) S Z 0 P 0 C
FD CB disp 2E SRA A, (IY+disp) S Z 0 P 0 C
FD CB disp 3E SRL A, (IY+disp) S Z 0 P 0 C
FD CB disp 01bbb110 BIT b, (IY+disp) ? Z 1 ? 0  
FD CB disp 10bbb110 RES b, (IY+disp)            
FD CB disp 11bbb110 SET b, (IY+disp)            
FD E1 POP IY            
FD E3 EX (SP), IY            
FD E5 PUSH IY            
FD E9 JP (IY)            
FD F9 LD SP, IY            
FE yy CP A, data S Z H OV 1 C
FF RST 38h            
Glossary
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
References