Slot 2 Mapping Mapped Code

Zool (SMS and GG versions) expects the VBlank bit (VDP status register bit 7) to be set several cycles before the VBlank IRQ actually occurs because of the following polling routine which can execute with interrupts enabled:

 wait_for_vblank:
    in a,(bf)
    and a,a
    jp p,wait_for_blank
    ret



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