Introduction

The Master System has 8KB of RAM.

The RAM appears in the Master System memory map from address $C000 to $DFFF and is mirrored from $E000 to $FFFF.

The entire 8KB can be used by game software. However, external peripherals are memory mapped and therefore need to be catered for.

Hardware

Inside the majority of Master Systems manufactured the 8KB RAM is implemented by a single NEC D4168 28-pin DIL I.C. Two more D4168 form the 16KB of dedicated VRAM.

From the datasheet:

The NEC uPD4168 is an 8,192 word by 8-bit NMOS XRAM designed to operate from a single +5V power supply. The NEC uPD4168 is termed an XRAM because it incorporates some of the best features of both SRAM (non-multiplexed addresses, simple interface requirements) and DRAMs (the one-transistor core cell provides high density at low cost).
The incorporation of an internal refresh address counter and refresh multiplexer allows the user to select one of three refresh modes. The self-refresh mode provides transparent refresh without system overhead. Internal latches for address, data, and chip select allow for use in systems incorporating multiplexed address/data buses.

The D4168 uses the JEDEC standard pinout used by 8KB SRAM and EPROM devices.

The Master System's simple memory mapping hardware based on address lines A14 and A15 maps the RAM in the last 16KB of the Z80 CPU memory map from $C000 to $FFFF when A14 and A15 are both 1 Because the RAM is only 8KB is size it appears mirrored in the second half of the 16KB address space.

The mirroring means that any memory writes to the last 16KB of the memory map in the range $C000 and $FFFF are written to RAM. It also means that any memory reads in the same address space read the RAM. This has a convenient side-effect that any writes to the cart mapping registers which are memory mapped between $FFFC to $FFFF and write-only can be read from RAM.

Bit 4 of I/O Port $3E must be 0 for RAM to be enabled. This feature allows the Master System 8KB of RAM to be disabled and RAM from an external device such as a cart to be used in the last 16KB of the memory map.

Software Development, Programming and Usage

To the programmer the RAM is simply seen as 8KB of RAM.

Because the Master System has dedicated VRAM and the PSG, VDP and other subsystems are I/O mapped and not memory mapped the entire 8KB can be used by game software.

Bit 4 of I/O Port $3E must be 0 for the RAM to be enabled. By default the RAM is always enabled by the Master System BIOS. However any access by games which manually write to I/O Port $3E must keep bit 4 cleared to keep RAM enabled.

External peripherals such as the Segascope 3D Glasses and cart memory mappers are memory mapped and need to be catered for when using RAM. These devices are memory mapped from $FFF8 to $FFFF. Other Sega development hardware was memory mapped in the $FFF0-$FFF7 range. Therefore software should keep the last 16 bytes of RAM free - $DFF0 to $DFFF and $FFF0 to $FFFF.

To ensure compatibility with known Master System hardware and peripherals game developers would initialise the stack pointer to $DFF0 and start allocating memory from the RAM base address $C000 and hope the two would never meet and cause a crash during runtime. (The Z80 has no stack management hardware other than the Stack Pointer register.)

Hardware Development, Programming and Usage

The fact that the RAM can be disabled allows some flexibility with developing hardware for the Master System because the RAM can be disabled and the last 16KB of the memory map is freed. For example an external 16KB of DRAM or SRAM can be mapped in doubling the size of available RAM. Disabling RAM can also allow other devices to be memory mapped to the same space of the memory map to allow access to memory mapped registers or buffers while RAM is temporarily disabled.

The D4168 uses the JEDEC standard pinout used by 8KB SRAM and EPROM devices so it can in theory be replaced by an 8KB SRAM I.C.

(TBC: the datasheet indicates that a pulse refresh can be performed when the CE line is high, which may allow for contents of RAM to be preserved when the RAM is disabled using I/O Port $3E - to be confirmed.)




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